JP2001273014A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a programmable controller that can maintain the cost standard for manufacturing with the technique of the present integrated circuit while the need of miniaturizing or a high-speed will be fulfilled. SOLUTION: The programmable controller is provided with an integrated circuit 10a for integrating an exclusive processor core 1' for performing sequence command, a command memory 4 for storing the sequence command and a data memory 5 being a working area during the performance of the sequence command into one chip.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a programmable controller.

[0002]

2. Description of the Related Art Generally, programmable controllers are widely used for controlling various devices. In recent years, the configuration of a device to be controlled has become complicated, and a high-speed operation has been required. Therefore, it is required to process a large number of input / output signals at a high speed. Therefore, as shown in FIG. 7, a dedicated processor 1 that performs a basic instruction process for executing a basic instruction which is a sequence instruction mainly for bit processing and an application instruction process for executing an application instruction which is a sequence instruction for a multi-bit operation is provided. By using it, high speed is realized,
A general-purpose processor 2 for controlling communication with external devices (communication processing), data exchange with peripheral devices (peripheral processing), and the like is provided separately from the special-purpose processor 1, and the special-purpose processor 1 and the general-purpose processor 2 perform parallel processing. Such a programmable controller has been proposed.

In such a programmable controller having a multiprocessor configuration (a programmable controller having a multiprocessor configuration in which a basic instruction and an application instruction are configured by different processors is disclosed in Japanese Patent Laid-Open No. 4-257002). At least part of the memory space is configured to be shared, so that necessary data on the memory can be referenced and updated when performing processing for basic instructions, processing for application instructions, communication processing, and peripheral processing. Has become. The memories used in the programmable controller include a system memory 3 for storing a system program, an instruction memory 4 for storing a sequence program composed of sequence instructions, and a data memory 5 necessary as a work area during execution of the sequence program. In a programmable controller capable of executing a differential instruction which is an instruction, a differential memory 6 serving as a data memory exclusively used for working with the differential instruction
It may be provided with. System memory 3 is the system RO
In many cases, both the M3a and the system RAM 3b are provided, and the system memory 3 is mainly used by the general-purpose processor 2. The instruction memory 4, data memory 5, and differential memory 6 are mainly used by the dedicated processor 1. The programmable controller is also provided with a peripheral IC 7 as a peripheral circuit unit for connecting peripheral devices such as a storage device, a printing device or a program creation device, and an input / output unit 8 for connecting various devices to be controlled.

[0004]

By the way, as described above, it has been required to process a large number of input / output signals at high speed, and the number of internal buses of the programmable controller tends to increase. In particular, the number of terminals of the dedicated processor 1 accessing a large number of memories has been significantly increased. Since there is a limit to the reduction of the pitch between terminals, an increase in the number of terminals results in an increase in the size of a dedicated processor package formed of an integrated circuit, which results in a problem that the mounting area increases. In many cases, the programmable controller is incorporated in a device to be controlled. In this type of programmable controller, an increase in the mounting area of the dedicated processor 1 is a factor that hinders miniaturization.

Although the operating speed of the dedicated processor 1 has been improved with the progress of miniaturization of the semiconductor process, the memory accessed by the dedicated processor 1 is provided separately from the dedicated processor 1. The path between 1 and the memory goes through a circuit board (such as a printed board), and the inductive component and the capacitive component of the circuit board hinder speeding up. That is, even if the speed of the dedicated processor 1 is increased, the access time to the memory cannot be reduced, and this access time may become a bottleneck that limits the overall speed of the programmable controller.

In order to solve this kind of problem, it is conceivable to integrate each element constituting the programmable controller on one chip. With the advance of the miniaturization technology of the semiconductor process, the circuit scale that can be integrated on one chip semiconductor is increasing. Given the remarkable trend, such a solution could be considered in the future. However, there is a problem in that if the entire programmable controller is integrated into one chip in the state of the art, the cost increases, which hinders commercialization.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to maintain the cost level for commercialization with current integrated circuit technology while satisfying the demand for miniaturization or high speed operation. Another object of the present invention is to provide a programmable controller having the above configuration.

[0008]

According to a first aspect of the present invention, there is provided a dedicated processor for executing a sequence instruction, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with external devices and peripheral devices, and a system program. The system includes a system memory for storage, a peripheral circuit unit for connecting external devices and peripheral devices, and a memory group used by a dedicated processor. The dedicated processor, the peripheral circuit unit, and the memory group are integrated on one chip. . According to this configuration, in the configuration of the programmable controller, a memory group that requires high-speed access with an increase in the processing speed of the dedicated processor is integrated on the same chip as the dedicated processor. An external circuit does not intervene in a path for accessing the memory group, so that higher-speed access is possible. In addition, the peripheral circuit portion, in which design resources are accumulated and relatively high-density integration is easy, is integrated into a dedicated processor and a single chip together with a memory group, so that even the current integrated circuit technology can avoid a significant increase in cost. However, the number of terminals of the integrated circuit can be significantly reduced, and the package mounting area of the integrated circuit can be reduced. As a result, the size of the programmable controller is reduced, and this is a particularly effective technical means for an embedded programmable controller.

According to a second aspect of the present invention, there is provided a dedicated processor that executes a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory that stores a system program, A peripheral circuit unit for connecting external devices and peripheral devices, and a memory group used by a dedicated processor, a differential memory used as a working memory when the dedicated processor executes a differential instruction that is a sequence instruction among the memory group. It is integrated on a single chip together with a dedicated processor. Differential memory is one for each word that the dedicated processor executes the differential instruction stored in the instruction memory.
Since it is allocated in bit width and requires an address bus of the same width as the instruction memory, the address bus can be reduced by integrating this differential memory on the same chip as the dedicated processor. However, the number of terminals of the package of the integrated circuit can be significantly reduced while avoiding a large increase in cost. As a result, the mounting area of the package of the integrated circuit can be reduced, which leads to downsizing of the programmable controller.

According to a third aspect of the present invention, there is provided a dedicated processor for executing a sequence instruction, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory for storing a system program, A peripheral circuit unit for connecting external devices and peripheral devices; and a memory group used by a dedicated processor. A data memory used as a work area when the dedicated processor executes a sequence instruction among the memory group is divided into two parts. One of the memories and a dedicated processor are integrated on one chip. According to this configuration, since the data memory is divided into two, it is possible to selectively use the data memory on the same chip as the dedicated processor and the external data memory according to the type of the sequence instruction executed by the dedicated processor. For example, when the number of accesses to the data memory increases even with one instruction, the access speed can be improved by using the data memory integrated on the same chip as the dedicated processor.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the one data memory has a wider data bus width than the other data memory. According to this configuration, since the data memory integrated on the same chip as the dedicated processor has a wider data bus width, the number of accesses can be reduced as compared with the case where an external data memory is used. Therefore, when one instruction requires multiple accesses to the data memory according to the type of the sequence instruction executed by the special purpose processor, the data memory integrated on the same chip as the special purpose processor is used. If the data memory is used, the execution speed of the sequence instruction can be increased as a whole.

A fifth aspect of the present invention provides a dedicated processor for executing a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with external devices and peripheral devices, a system memory for storing a system program, It comprises a peripheral circuit section for connecting external devices and peripheral devices, and a memory group used by a dedicated processor, wherein the dedicated processor and the peripheral circuit section are integrated on one chip. According to this configuration, the peripheral circuit section in which design resources are stored and relatively high-density integration is easy is integrated into a dedicated processor and a single chip together with a memory group. The number of terminals as an integrated circuit can be reduced while avoiding an increase in the number of terminals, and the mounting area of the package of the integrated circuit can be reduced, which leads to downsizing of the programmable controller.

According to a sixth aspect of the present invention, there is provided a dedicated processor for executing a sequence instruction, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory for storing a system program, A peripheral circuit unit for connecting external devices and peripheral devices, a communication management buffer having an error detection function for data received through the peripheral circuit unit, and a memory group used by the dedicated processor; The management buffer is integrated on one chip. According to this configuration, the peripheral circuit section in which design resources are stored and relatively high-density integration is easy is integrated into a dedicated processor and a single chip together with a memory group. The number of terminals as an integrated circuit can be reduced while avoiding an increase in the number of terminals, and the mounting area of the package of the integrated circuit can be reduced, which leads to downsizing of the programmable controller. In addition, since the communication management buffer detects errors in the received data, the load on the general-purpose processor can be reduced, the cost can be reduced by using a low-speed processor as a general-purpose processor, or the surplus of the capability generated in the general-purpose processor can be used. Different functions can be realized.

According to a seventh aspect of the present invention, in the first to sixth aspects of the present invention, the memory group is used as an instruction memory storing a program composed of sequence instructions, and as a work area when a dedicated processor executes the sequence instructions. And a data memory to be used.

According to an eighth aspect of the present invention, in the first to seventh aspects of the present invention, a bus interface unit for access control is connected to the bus of the dedicated processor, and the peripheral circuit unit, the general-purpose processor, and the memory group are connected. It is connected to a dedicated processor via a bus interface unit.

In a ninth aspect of the present invention, in the first to eighth aspects, the dedicated processor performs a pipeline operation.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) In this embodiment, a peripheral IC for connecting peripheral devices (see reference numeral 7 in FIG. 7).
In view of the fact that design resources have been accumulated in a form that can be reused for circuits corresponding to the above, the dedicated processor, a memory mainly accessed by the dedicated processor, and a function corresponding to a peripheral IC are integrated into one chip, An example in which miniaturization and high speed can be achieved will be described.

That is, in this embodiment, as shown in FIG. 1, a circuit corresponding to the dedicated processor 1 having the conventional configuration shown in FIG. 7 is a dedicated processor core 1 ', and corresponds to a peripheral IC 7 which is a peripheral circuit unit. Using the circuit as a functional core 7 ′, together with the instruction memory 4, data memory 5, and differential memory 6,
This constitutes a one-chip integrated circuit 10a as an SI. Dedicated processor core 1 'in the present embodiment
Corresponds to a “dedicated processor” in the claims. Further, a bus interface unit (hereinafter, referred to as “BIU”) 9 is also mounted on the integrated circuit 10a. The BIU 9 is a circuit for controlling access to the inside and outside of the integrated circuit 10a. That is, the dedicated processor core 1 ′ includes an instruction memory 4, a data memory 5, a differential memory 6 provided inside the integrated circuit 10 a via the BIU 9,
The general-purpose processor 2, the system memory 3, and the input / output unit 8 provided outside the integrated circuit 10 a are also connected to the BIU 9.

With such a configuration, the integrated circuit 10a
The power supply terminal may be provided in addition to the terminal connected to the bus between the general-purpose processor 2, the terminal connected to the input / output unit 8, and the terminal connected to the peripheral device. , The number of terminals of the integrated circuit 10a is greatly reduced. As a result, the package area of the integrated circuit 10a is
Can be smaller than the package area of
As a result, the size of the programmable controller is reduced. Moreover, the instruction memory 4, data memory 5, and differential memory 6, which are accessed mainly by the dedicated processor 1, are connected to the dedicated processor core 1 'by the internal wiring of the integrated circuit 10a.
, The access speed can be improved as compared with the case where an external circuit board is used.

The concept of the access speed is shown in FIG. FIG. 2A shows the operation of the dedicated processor 1 in the conventional configuration, and FIG. 2B shows the operation of the dedicated processor core 1 'in the present embodiment. The special-purpose processor 1 and the special-purpose processor core 1 'have the same function, and have a five-stage pipeline configuration in which instruction execution processing is divided into five stages. That is, the instruction execution process is performed in five stages: instruction fetch IF, instruction decode ID, instruction execution EX, memory access MEM, and result write WB. In the pipeline operation, the processing time of each stage (the execution time of the pipeline stage) needs to be equal.
Conventionally, the time required for the instruction execution EXE stage is the longest among the five stages described above, and this time defines the entire pipeline cycle of the dedicated processor 1 (dedicated processor core 1 '). However, as the miniaturization of the semiconductor process advances and the operation speed of the circuit increases, the time required for the instruction execution EXE is shortened. Therefore, the instruction fetch ID required to access the memory and the time required for the memory access MEM stage are required. Is the element that defines the pipeline cycle. In other words, in the conventional configuration, the circuit cycle is included in the access path from the dedicated processor 1 to the memory, so that the pipeline cycle is relatively long as shown in FIG. Since the access path to the memory is formed inside the integrated circuit 10a, the pipeline cycle is shorter than in the conventional configuration as shown in FIG. 2B. Other configurations and operations are the same as those of the conventional configuration.

(Second Embodiment) In this embodiment, FIG.
As shown in the figure, the differential memory 6 is integrated with the dedicated processor core 1 'in the integrated circuit 10b. Also,
The integrated circuit 10b has a BIU 9 as in the first embodiment.
Is provided. Instruction memory 4, data memory 5, peripheral I
C7 is provided outside the integrated circuit 10b. That is, compared to the conventional configuration, only the differential memory 6 is integrated with the dedicated processor 1 on one chip.

Generally, the data width of the differential memory 6 is 1 bit, but since the differential memory 6 has the same address space as the instruction memory 4, the address width is the same as that of the instruction memory 4. Therefore, by mounting only the differential memory 6 on the integrated circuit 10b together with the dedicated processor core 1 ', the number of terminals of the package of the integrated circuit 10b can be reduced as compared with the package of the dedicated processor 1 having the conventional configuration. Here, since the address spaces of the instruction memory 4 and the differential memory 6 are equal, the address bus is connected to the instruction memory 4.
And dedicated memory 6 to share dedicated processor 1
It is conceivable to reduce the number of terminals. However, if such a configuration is adopted, when it becomes necessary to access different addresses in the instruction memory 4 and the differential memory 6 at the same time, the access to one of the memories is invalidated. The exceptional processing of shifting the invalidated processing to the next pipeline cycle is required, so that the time required for executing the instruction increases. In the present embodiment, it is possible to reduce the number of terminals of the integrated circuit 10b from the number of terminals of the conventional dedicated processor 1 while maintaining the execution time of an instruction substantially equal to that of the conventional configuration without performing such exceptional processing. You can. Other configurations and operations are the same as those of the conventional configuration.

(Third Embodiment) This embodiment is different from FIG.
As shown in the figure, two data memories 5a and 5b are provided,
This constitutes an integrated circuit 10c in which one data memory 5b is integrated on the same chip as the dedicated processor core 1 'and BIU9.

As described in the first embodiment, the dedicated processor core 1 'basically executes an instruction by a five-stage pipeline operation. In some cases, execution of one instruction may require more steps.

For example, an output instruction is sent to data memory 5 (5
a, 5b) is an instruction to update a specific bit in the conventional configuration. In the conventional configuration, data is read from the data memory 5 in word units, and after updating the target bit, the data is written back to the data memory 5 in word units. This is the process.
That is, to execute the output instruction, the data memory 5 is accessed twice. Therefore, when executing an instruction in which one instruction accesses the data memory 5 a plurality of times, the execution of the subsequent instruction is suspended, and the exception processing for accessing the data memory 5 as many times as necessary is executed. Is required. Such instructions do not require the data memory 5 to be accessed twice, but some instructions need to be accessed many times, and the execution of such instructions requires a lot of time. In particular, a lot of information is required to execute a timer instruction or a counter instruction. If this type of information is 48 bits and the word width of the data memory 5 is 16 bits, 3 Times access is required. In other words, as shown in FIG. 5A, reading and writing are performed three times, and the execution of this type of instruction requires more than five steps.

In this embodiment, however, the data memory 5b is integrated on the same chip as the dedicated processor core 1 '.
By setting the width of the data bus wider than that of the external data memory 5a, the number of accesses to the data memory 5b by the timer instruction or the counter instruction can be reduced. For example, in the above-described example, by setting the data bus of the data memory 5b to 48 bits, an instruction which conventionally required reading and writing three times each becomes one instruction as shown in FIG. It is sufficient to read and write each time, and the execution time of the instruction can be greatly reduced. That is, the processing can be speeded up by selectively using the external data memory 5a and the internal data memory 5b of the integrated circuit 10c in accordance with the instruction executed by the dedicated processor core 1 '. Other configurations and operations are the same as those of the conventional configuration.

(Fourth Embodiment) This embodiment is different from FIG.
As shown in the figure, a functional core 7 'corresponding to a peripheral IC in the conventional configuration is integrated into a single chip together with a dedicated processor core 1'. The BIU 9 and the communication management buffer 11 are provided in the integrated circuit 10d provided with the dedicated processor core 1 '.
Are also integrated. The communication management buffer 11 has a function core 7 '
This reduces the load on the general-purpose processor 2 when communicating with an external device via the IC, and makes it possible to determine an error in received data during communication within the integrated circuit 10d.

Generally, the received data includes a header indicating communication contents and a determination bit string for determining whether the received data has been destroyed by the influence of noise or the like. In step 11, whether or not the header is normal is determined based on the determination bit string, and whether or not the content of the header complies with the communication protocol is determined. Here, when the communication management buffer 11 detects inadequacy of the content of the determination bit string or the content of the header, the function core 7 'immediately returns an error to the external device. When the communication management buffer 11 determines that the received data is normal, the communication management buffer 11 notifies the general-purpose processor 2 that the received data exists. As described above, since it is not necessary for the general-purpose processor 2 to perform the error determination of the received data, the load on the communication processing in the general-purpose processor 2 is reduced. In addition, since the load on the communication processing of the general-purpose processor 2 is reduced, the communication function can be expanded with the surplus processing capacity of the general-purpose processor 2. Other configurations and operations are the same as those of the conventional configuration.

In the configuration of the present embodiment, the number of components is reduced by incorporating the functional core 7 'corresponding to the peripheral IC into the integrated circuit 10d as compared with the conventional configuration, so that the mounting area is reduced. This leads to smaller programmable controllers.

It should be noted that the configurations of the above-described embodiments can be used in appropriate combinations.

[0031]

According to the first aspect of the present invention, there is provided a dedicated processor for executing a sequence instruction, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with external devices and peripheral devices, and a system memory for storing a system program. And a peripheral circuit unit for connecting external devices and peripheral devices, and a memory group used by the dedicated processor, wherein the dedicated processor, the peripheral circuit unit, and the memory group are integrated on one chip. According to this configuration, in the configuration of the programmable controller, a memory group that requires high-speed access with an increase in the processing speed of the dedicated processor is integrated on the same chip as the dedicated processor. An external circuit does not intervene in a path for accessing the memory group, so that higher-speed access is possible. In addition, the peripheral circuit portion, in which design resources are accumulated and relatively high-density integration is easy, is integrated into a dedicated processor and a single chip together with a memory group, so that even the current integrated circuit technology can avoid a significant increase in cost. However, the number of terminals of the integrated circuit can be significantly reduced, and the package mounting area of the integrated circuit can be reduced. As a result, the size of the programmable controller is reduced, and this is a particularly effective technical means for an embedded programmable controller.

According to a second aspect of the present invention, there is provided a dedicated processor that executes a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory that stores a system program, A peripheral circuit unit for connecting external devices and peripheral devices, and a memory group used by a dedicated processor, a differential memory used as a working memory when the dedicated processor executes a differential instruction that is a sequence instruction among the memory group. It is integrated on a single chip together with a dedicated processor. Differential memory is one for each word that the dedicated processor executes the differential instruction stored in the instruction memory.
Since it is allocated in bit width and requires an address bus of the same width as the instruction memory, the address bus can be reduced by integrating this differential memory on the same chip as the dedicated processor. However, the number of terminals of the package of the integrated circuit can be significantly reduced while avoiding a large increase in cost. As a result, the mounting area of the package of the integrated circuit can be reduced, which leads to downsizing of the programmable controller.

According to a third aspect of the present invention, there is provided a dedicated processor that executes a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory that stores a system program, A peripheral circuit unit for connecting external devices and peripheral devices; and a memory group used by a dedicated processor. A data memory used as a work area when the dedicated processor executes a sequence instruction among the memory group is divided into two parts. One of the memories and a dedicated processor are integrated on one chip. According to this configuration, since the data memory is divided into two, it is possible to selectively use the data memory on the same chip as the dedicated processor and the external data memory according to the type of the sequence instruction executed by the dedicated processor. For example, when the number of accesses to the data memory increases even with one instruction, the access speed can be improved by using the data memory integrated on the same chip as the dedicated processor.

According to a fourth aspect of the present invention, in the third aspect of the present invention, the one data memory has a wider data bus width than the other data memory. According to this configuration, since the data memory integrated on the same chip as the dedicated processor has a wider data bus width, the number of accesses can be reduced as compared with the case where an external data memory is used. Therefore, when one instruction requires multiple accesses to the data memory according to the type of the sequence instruction executed by the special purpose processor, the data memory integrated on the same chip as the special purpose processor is used. If the data memory is used, the execution speed of the sequence instruction can be increased as a whole.

According to a fifth aspect of the present invention, there is provided a dedicated processor for executing a sequence instruction, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory for storing a system program, It comprises a peripheral circuit section for connecting external devices and peripheral devices, and a memory group used by a dedicated processor, wherein the dedicated processor and the peripheral circuit section are integrated on one chip. According to this configuration, the peripheral circuit section in which design resources are stored and relatively high-density integration is easy is integrated into a dedicated processor and a single chip together with a memory group. The number of terminals as an integrated circuit can be reduced while avoiding an increase in the number of terminals, and the mounting area of the package of the integrated circuit can be reduced, which leads to downsizing of the programmable controller.

According to a sixth aspect of the present invention, there is provided a dedicated processor for executing a sequence instruction, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory for storing a system program, A peripheral circuit unit for connecting external devices and peripheral devices, a communication management buffer having an error detection function for data received through the peripheral circuit unit, and a memory group used by the dedicated processor; The management buffer is integrated on one chip. According to this configuration, the peripheral circuit section in which design resources are stored and relatively high-density integration is easy is integrated into a dedicated processor and a single chip together with a memory group. The number of terminals as an integrated circuit can be reduced while avoiding an increase in the number of terminals, and the mounting area of the package of the integrated circuit can be reduced, which leads to downsizing of the programmable controller. In addition, since the communication management buffer detects errors in the received data, the load on the general-purpose processor can be reduced, the cost can be reduced by using a low-speed processor as a general-purpose processor, or the surplus of the capability generated in the general-purpose processor can be used. Different functions can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

2 (a) is an operation explanatory diagram of a conventional example, and FIG. 2 (b) is an operation explanatory diagram of the configuration shown in FIG. 1;

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a third embodiment of the present invention.

5 (a) is an operation explanatory diagram of a conventional example, and FIG. 5 (b) is an operation explanatory diagram of the configuration shown in FIG. 4;

FIG. 6 is a block diagram showing a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Dedicated processor 1 'Dedicated processor core 2 General purpose processor 3 System memory 4 Instruction memory 5 Data memory 5a, 5b Data memory 6 Differential memory 7 Peripheral IC 7' Function core 8 Input / output unit 9 Bus interface unit 10a to 10d Integrated circuit 11 Communication Management buffer

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B045 AA00 AA05 GG06 KK07 KK08 5H220 BB01 BB03 CC02 EE01 EE04 EE07 EE11 FF01 FF03 JJ12 JJ34 9A001 BB01 BB05 BB05

Claims (9)

[Claims] A dedicated processor that executes a sequence instruction; a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device; a system memory that stores a system program; And a memory group used by a dedicated processor, wherein the dedicated processor, the peripheral circuit unit, and the memory group are integrated on a single chip. 2. A dedicated processor that executes a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory that stores a system program, and an external device and a peripheral device And a memory group used by a special purpose processor, and a differential memory used as a working memory when the special purpose processor executes a differential instruction among the sequence instructions is included in the memory group together with the special purpose processor. A programmable controller characterized by being integrated on a chip. 3. A dedicated processor for executing sequence instructions, a general-purpose processor which operates in parallel with the dedicated processor and controls data exchange with external devices and peripheral devices, a system memory for storing system programs, and external devices and peripheral devices And a memory group used by a dedicated processor. A data memory used as a work area when the dedicated processor executes a sequence instruction is divided into two, and one of the data memories is A programmable controller, wherein the processor and the processor are integrated on one chip. 4. The programmable controller according to claim 3, wherein the one data memory has a wider data bus width than the other data memory. 5. A dedicated processor that executes a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory that stores a system program, and an external device and a peripheral device And a memory group used by the dedicated processor, wherein the dedicated processor and the peripheral circuit unit are integrated on one chip. 6. A dedicated processor that executes a sequence instruction, a general-purpose processor that operates in parallel with the dedicated processor and controls data exchange with an external device and a peripheral device, a system memory that stores a system program, and an external device and a peripheral device , A communication management buffer having a function of detecting an error of received data received through the peripheral circuit, and a memory group used by the dedicated processor, wherein the dedicated processor, the peripheral circuit, and the communication management buffer have one. A programmable controller characterized by being integrated on a chip. 7. The memory system according to claim 1, wherein said memory group includes an instruction memory storing a program composed of sequence instructions, and a data memory used as a work area when the dedicated processor executes the sequence instructions. Item 7. The programmable controller according to any one of items 6. 8. A bus interface unit for access control is connected to a bus of the dedicated processor, and a peripheral circuit unit, a general-purpose processor, and a memory group are connected to the dedicated processor via the bus interface unit. The programmable controller according to any one of claims 1 to 7, wherein 9. The programmable controller according to claim 1, wherein the dedicated processor performs a pipeline operation.