JPS6349816B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal arithmetic device that achieves high-speed arithmetic operations and is also compact and highly reliable.

Generally, when performing calculations on digital signals, the first
There is a system with the configuration shown in Figure A. In this diagram,
When a command is sent from the program memory section 1 to the central control section 2, the central control section 2 performs address calculation to determine the address of the memory section 3, inputs the signal from the memory section 3, and performs the calculation. This calculation result is also subjected to address calculation to determine the address of the memory section 3 to be stored and transferred to the memory section 3. Further, the input/output of signals is also controlled and input/output in the central control section 2 via the interface section 4. In such a system, the central control section 2 must perform memory address calculation and input/output control in addition to signal calculation, and has the drawback that the signal calculation speed cannot be increased.

In order to improve this method and speed up the calculation,
As shown in the block diagram of FIG. 1B, there is a method in which the calculation section 7 is made independent and is responsible only for signal calculations, and the control section 6 performs memory address calculations and input/output control. According to this method, the calculation speed can be increased, but if the calculation speed is increased, the control becomes complicated, and the control section 6 becomes larger than the calculation section 7. This arithmetic unit 7 executes addition, subtraction, multiplication, and logical operations in any arithmetic device, and has the advantage of being versatile and made of LSI. However, compared to the arithmetic unit 7, the control unit 6 is If it is large, it has the disadvantage that even if the arithmetic unit 7 is made of LSI, the overall size cannot be reduced very much.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital signal calculation device that solves these drawbacks and realizes high-speed calculation, miniaturization, and high reliability of the device.

The configuration of the digital signal processing device of the present invention uses a plurality of identical microprocessor chips each having a processing function based on instructions, and performs signal processing, memory address processing, and input/output control in parallel. a memory address calculation chip, an input/output control chip, a program memory section that provides calculation instructions to each of these chips, and a memory address calculation chip that corresponds to the address output from the memory address calculation chip in accordance with the instructions from the program memory section. a memory unit that outputs predetermined storage information;
The present invention is characterized by comprising an input circuit for giving commands to the program memory section using a program memory up signal or a start signal output from the memory address calculation chip.

In the present invention, the conventional central control section and interface section are replaced with a memory address calculation chip.
Three identical LSIs: calculation chip and input/output chip
It consists of a microprocessor chip, and each of these
Since LSI chips have processing functions based on external instructions, signal calculations, memory address calculations, and input/output control can be executed in parallel to speed up calculations. This makes the device more compact and highly reliable.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the present invention. Arithmetic instructions from program memory section 1 are sent to memory address arithmetic chip 1 through a common instruction bus.
1, is sent to the arithmetic chip 12 and input/output chip 13. These memory address calculation chip 11, calculation chip 12, and input/output chip 13 are composed of LSI chips of the same microprocessor, and these LSI chips are, for example, commercially available 16-bit microprocessors.
It is assumed that the computer has a function of converting commands from the computer into internal control signals and performing processing such as calculation, judgment, and transfer. Also, the memory address calculation chip 11 operates in the memory section 3 in response to instructions from the program memory section 1.
This is the part that calculates the address of the signal to be read and written and sends it to the memory section 3. As a simple example, when performing an iterative operation such as Y= _N 〓 ^K=1 (X _K + Z _K ), if X _K and Z _K are stored in the order in the memory section 3, then This memory address calculation chip 11 increments the address by 1 for each calculation, and when the execution of one instruction is completed and the memory address calculation is completed, this memory address calculation chip 11 adds an OR circuit to the program memory section 1. A program memory up signal is sent through the gate 14 of the program to advance the program by one. In addition,
A start signal is also input to the program memory section 1 via the gate circuit 14.

The memory section 3 reads or writes signals according to the memory address from the memory address calculation chip 11. Furthermore, the arithmetic chip 12 operates on the signal from the memory section 3 according to the command from the program memory section 1, and sends the result to the memory section 3.
Store in. Furthermore, when an input/output command is received from the program memory section 1, the input/output chip 13
It performs signal input/output between the outside and the memory section 3.

FIG. 3 is a block diagram of an example of an LSI chip used in the present invention. The input signal is input to an input buffer circuit 21. This input buffer circuit 21 has a two-stage configuration, and while a signal is being sent from one buffer to the arithmetic and logic circuit 22, the other buffer receives the next input signal. Further, the arithmetic and logic circuit 22 performs arithmetic or logical judgment on the signal and sends it to the output buffer circuit 23 . This output buffer circuit 23 has the same two-stage configuration as the input buffer circuit 21, and simultaneously performs external transfer, calculation, and signal reception from the logic circuit 22. Further, to control each circuit, an internal program circuit 24 converts a command from the program memory section into a control signal, and sends it to each section according to the clock timing of a timing circuit 25 for execution.

When this LSI chip is used as the input/output chip 13 and the signal is not operated, the command transfers the signal from the input buffer circuit 21 to the output buffer circuit 23, temporarily holds the signal, and transfers the signal from the output buffer circuit 23 to the external circuit. Send to. Further, the counter circuit 26 is used for counting the number of repeated operations, such as when used as the memory address arithmetic chip 11.

As explained above, the present invention improves the speed of calculation by configuring one calculation device using three identical LSI chips: a signal calculation chip, a memory address calculation chip, and an input/output chip. Since the device can be realized using only an LSI chip, a memory, and some peripheral circuits, it is possible to achieve miniaturization and high reliability, and by using the same LSI chip, there is also the effect of achieving general-purpose LSI chips.

[Brief explanation of drawings]

1A and 1B are block diagrams of a conventional digital signal calculation device, FIG. 2 is a block diagram of an embodiment of the present invention, and FIG. 3 is a block diagram of an example of the LSI used in FIG. In the figure: 1...Program memory section, 2...Central control section, 3...Memory section, 4...Interface section, 6...Control section, 7...Calculation section, 11...Memory address calculation chip, 12 ...Arithmetic chip, 1
3...Input/output chip, 14...Gate circuit, 21
... Input buffer circuit, 22 ... Arithmetic and logic circuit, 23 ... Output buffer circuit, 24 ... Internal program circuit, 25 ... Timing circuit, 26 ...
...A counter circuit.

Claims (1)

[Scope of Claims] 1. A signal operation chip and a memory address in which a plurality of identical microprocessor chips each having a processing function based on instructions are used to perform signal operation, memory address operation, and input/output control in parallel, respectively. an arithmetic chip and an input/output control chip; a program memory section that provides arithmetic instructions to each of these chips; and a program memory section that stores predetermined storage information corresponding to the address output from the memory address arithmetic chip in accordance with the instructions from the program memory section. What is claimed is: 1. A digital signal calculation device comprising: a memory unit for outputting data; and an input circuit for giving commands to the program memory unit using a program memory up signal or a start signal output from the memory address calculation chip.