JPS61153770A - Image processor - Google Patents

Abstract

PURPOSE:To execute access at a high speed to an image memory for storing an image signal, by connecting plural buses to a storage means for storing image information. CONSTITUTION:In addition to a general-purpase system bus 213, an image bus 214 is provided separately. An image memory 203 is connected to both the buses, and access from both the buses can be executed. An image reading part 201 and an image recording part 207 are connected to the system bus 213 through the bus 214 and the image memory 203, therefore, a high-speed multiple image signal can be processed without being influenced at all by an operation of a CPU208 side of low speed.

Description

TECHNICAL FIELD The present invention relates to an image processing apparatus, and particularly to an image processing apparatus having a memory for storing image information.

E. Prior Art" FIG. 1 is a circuit block diagram for explaining the prior art. In FIG. . On the other hand, 107 is a dual image storage unit, and the image memory 103
The image signal stored in the image signal is read out and recorded as a visible image. A basic copy operation is possible using the portions described above.

Furthermore, at the time of transmission, an image signal is read out from the one-image memory 103 and sent to the image compression/expansion section 104, where the redundancy of the image signal is compressed, and then sent out to the line via the line control section 105.

Upon reception, the redundancy-compressed data received via the line control section 105 is expanded by the image compression/expansion section 104 and stored in the image memory 103.

In addition, CPU108, ROM109, RAMll0
, character generator (hereinafter abbreviated as CG) 111.
and the calendar 112 etc. are connected to the system bus 113 (hereinafter referred to as M
Since the image signals are connected via a BUS (abbreviated as BUS), it is possible to ambiguous image signals such as adding a date or text information to the image signals in the memory.

In this way, in the conventional configuration, each element is connected via the MBUS 113 of the CPU 108.

However, in general, the image reading section 101 or the image recording section 107
The image signals handled by the system are often large in volume and high speed.
On the other hand, character data and calendar information handled via the CPU 108 are slow and require a long time to use the MBUS 13.

Furthermore, the use of MBUS l 13 by these I10 devices is limited to the use of MBUS l 11 by the program execution of the CPU 108.
It also conflicts with the use of 3.

In this way, during the period when elements operating at low speed use MBUSII3, the image reading unit 101 and image recording unit 107 use MBUSII3.
The image memory cannot be accessed via the USl 13, which makes it difficult for the entire device to operate at high speed.

The present invention was made in view of the above-mentioned drawbacks of the prior art.
The purpose is to provide an image processing device that has a bus that allows high-speed access to an image memory that stores image signals.

E Example” FIG. 882 shows an embodiment of the present invention.

In this embodiment, a general-purpose system bus 213 (
In addition to the image bus 214 (hereinafter referred to as VBUS)
) are provided separately. The image memory 203 is connected to both buses and can be accessed from both. However, image reading! 5201. And image recording unit 2074tVBUS214 and image 11%!
Since it is connected to the MBUS 203 via J203, it is possible to process a large amount of high-speed image signals without being affected by the operation of the low-speed CPU 208.

The image memory 20 is also
It is possible to speed up image processing without deteriorating the usage efficiency of 3.

Furthermore, as shown by the WR line in FIG. 2, it is clear that the two-bus system of this embodiment is also effective when the DMAC (direct memory access controller) 215 is connected to the MBUS.

That is, originally, during DMA operation, elements other than the data transfer source and transfer destination lose the right to use the bus.
According to this embodiment, the elements on the VBUS 214 side can always access the image memory 203, and the operating efficiency of the entire device can be dramatically improved.

L effect" As explained above, according to the present invention, by providing another 7 heses in one image memory, the access paths to the two image memories are duplicated, so there is no delay in image processing due to bus occupancy. , it is possible to speed up image processing.

[Brief explanation of the drawing]

FIG. 1 is a block circuit diagram explaining a conventional example, and FIG. 2 is a block circuit diagram of an embodiment of the present invention. In the figure, 201... Image reading unit, 203... Image memory, 208... CPU, 209... ROM, 210
...RAM, 213...MBUS, 214...V
BUS. 215...DMAC.

Claims (2)

[Claims] (1) An image processing device having a storage means for storing image information and a plurality of buses connected to the storage means. (2) The image input/output means further includes an image input/output means and a logic operation control means, and the image input/output means is connected to the first bus of the plurality of buses connected to the storage means, and the logic operation control means is connected to the first bus of the plurality of buses connected to the storage means. The image processing device according to claim 1, wherein the image processing device is connected to a second bus of the plurality of buses.