JP3357693B2 - Emulation memory mapping circuit and emulation system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mapping circuit of an emulation memory in an in-circuit emulator, and more particularly to a mapping circuit most suitable for an emulation memory corresponding to a target processor which accesses the memory at high speed.

[0002]

2. Description of the Related Art In an in-circuit emulator, as a substitute for a memory accessed by a target processor,
Provides emulation memory. In such an emulation memory, in order to be as close as possible to the configuration of the memory originally accessed by the processor,
A mapping process for allocating an arbitrary address to the emulation memory is performed.

FIG. 3 is a diagram showing a configuration of a mapping circuit for performing the above-described mapping process and its surroundings.

[0004] In FIG. 3, a mapping circuit 51 has one of all address spaces of an emulation memory 52.
One address area, for example, only one page is mapped. When the target processor 53 accesses a memory (not shown), the upper side of the address signal is compared with a mapping address externally set in a register 54 provided in the mapping circuit 51, and when both match, The hit signal (HIT #) is given from the mapping circuit 51 to the emulation memory 52 as an enable signal of the emulation memory 52, assuming that the memory access of the target processor 53 is assigned to the emulation memory 52. As a result, the emulation memory 52 becomes accessible, and the emulation memory 52 is accessed on the lower side of the address signal output from the target processor 53.

FIG. 4 is a diagram showing a specific circuit configuration of a comparison circuit that performs the above-described comparison operation in the mapping circuit shown in FIG.

In FIG. 4, in a comparison circuit 55, the upper n bits (A ₀ -A _{n -1} ) of the address signal output from the target processor 53 and the mapping address set in the register 54 are exclusive. The comparison is made by a NOR (EX-NOR) gate 56, and when it is detected by a NAND (NAND) gate 57 that all the comparison results by the respective EX-NOR gates 56 match, a hit signal is output to the enable signal ( CS #)
Is output as

In the mapping circuit 51 provided with such a comparison circuit 55, the mapping address is stored in the register 54 only for one page of the emulation memory 52.
, It is not possible to perform mapping processing on multiple pages. Therefore, in order to perform mapping processing on a plurality of pages, a plurality of configurations shown in FIG. 4 must be prepared. Therefore, in such a case,
The use efficiency of the circuit area in the emulation memory and the mapping circuit becomes extremely poor, and the circuit scale increases.

Therefore, as a mapping circuit 58 for mapping a plurality of pages without increasing the circuit scale of the emulation memory, for example, FIG. 6 showing a specific configuration of the mapping circuit 58 shown in FIG. 5 and FIG.
There is something like that shown in

In FIG. 5 and FIG. 6, a mapping address set for each page by a mapping address setting circuit 61 is stored in a register 60 of a comparison circuit 59 corresponding to each of a plurality of pages to be mapped. The upper side of the address signal is compared by each comparison circuit 59. When the priority encoder 62 detects that any one of the comparison circuits 59 matches, it is given to the hit signal (HIT #) emulation memory 52. The upper side (a ₀ , a ₁ ) of the address signal indicating the page of the emulation memory 52 selected corresponding to the matching comparison circuit 59 is given to the emulation memory 52 as a page selection address.

In such a configuration, since a plurality of pages are selected by the priority encoder 62, the circuit area can be effectively used without preparing a plurality of emulation memories 52.

However, in the configuration shown in FIG. 6, the hit signal and the page selection address (a ₀ , a
_In order to obtain ₁ ), that is, in order for the emulation memory 52 to be accessed, the processing time of the priority encoder 62 in addition to the comparison circuit 59 is required.

For example, when the comparison circuit 59 is composed of an EX-NOR gate 56 and a NAND gate 57 as shown in FIG. 4, the delay time of the EX-NOR gate 56 corresponds to two stages of logic gates. Then, in order to obtain a hit signal, the sum of the delay time of three logic gates in the comparison circuit 59 and the delay time of at least one logic gate in the priority encoder 62 is calculated.
A delay time corresponding to a stage is required.

For this reason, the access time of the emulation memory 52 becomes long, and it has been extremely difficult to cope with a high-speed memory access in the target processor.

[0014]

As described above,
In the configuration of the conventional mapping circuit shown in FIGS. 3 and 4, when trying to map a plurality of pages of the emulation memory, the utilization efficiency of the circuit area deteriorates and the configuration becomes large.

On the other hand, in the configuration of the conventional mapping circuit shown in FIG. 5 and FIG. 6, the enlargement of the configuration can be avoided, but the access speed of the emulation memory is reduced.

That is, in either configuration, it has not been possible to avoid both the enlargement of the configuration and the delay of the access speed.

Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a mapping of an emulation memory capable of satisfying both the downsizing of the configuration and the increase in the access speed of the emulation memory. It is to provide a circuit.

[0018]

In order to achieve the above object, a first means for solving the problem is to provide a plurality of buffer inverters for receiving an address given from a target processor and outputting the address as a buffer or inverting the buffer. Circuit, a plurality of first logic gates for receiving a buffer output or an inverted output of the buffer inverter circuit and performing a logical operation on the buffer output or the inverted output, and an emulation memory for receiving an output of the first logic gate A second logic gate for generating and outputting a first selection signal for selecting an emulation memory from among the addresses provided from the target processor in response to the output of the first logic gate. The emulation set in advance corresponding to a mapping address to be mapped to And a third logic gate for generating and outputting a second selection signal for selecting and specifying an address area of the memory, wherein a combination of a buffer output or an inverted output of the buffer inverter circuit applied to the first logic gate is programmable. When a PLD (programmable logic device) to be changed and a mapping address to be mapped to the emulation memory for a memory access of the target processor are changed, a mapping address to be newly mapped to the emulation memory is changed. An input circuit for inputting, a conversion circuit for converting a mapping address provided from the input circuit into connection information for determining a combination of an output or an inverted output of the buffer inverter circuit provided to the first logic gate, and the conversion circuit Thus according to the obtained connection information, and having a PLD write circuit for changing the combination of the output or the inverted output of the buffer inverter circuit applied to said first logic gate.

The second means includes a target processor which accesses a memory by outputting an address by executing a program, an emulation memory acting as a substitute for the memory accessed by the target processor, and a mapping circuit of the first means. It is characterized by having.

[0020]

The first means activates an emulation memory by a buffer inverter circuit and a signal generated through three stages of logic gates, a first logic gate and a second logic gate. A buffer inverter circuit that selects and specifies an address area of an emulation memory mapped by a signal generated through a first logic gate and a third logic gate, and is provided to an output of the first logic gate according to a mapping address. By setting the combination of the outputs in a programmable manner, the address area of the emulation memory to be mapped can be set arbitrarily.

The second means maps the address of the memory accessed by the target processor to the emulation memory by the mapping circuit of the first means.

[0022]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a system including a mapping circuit of an emulation memory according to an embodiment of the present invention.

In FIG. 1, the emulation system is a PLD (programmable logic device)
1. A mapping circuit including a mapping address input circuit 2, a connection information conversion circuit 3, and a PLD writing circuit 4, an emulation memory 5 mapped by the mapping circuit, and a target processor 6 accessing the emulation memory 5. Have been.

The PLD 1 receives, at the input terminals I0 to I7, the higher-order 8-bit address signal of the address signals output from the target processor 6, and says that the content of the address signal from the target processor 6 is valid. Address strobe signal (AS)
#) At the input terminal I8 and the emulation memory 5
Enable signal (C
S #) is output from the output terminal O0 to the emulation memory 5, and the page numbers (a ₀ , a ₁ ) for selecting and specifying the four mapped address areas in all the address spaces of the emulation memory 5 are output to the output terminal O1. , O2 to the emulation memory 5.

The PLD 1 is constituted by a combination of logic gates, for example, as shown in FIG.

In FIG. 2, a PLD 1 receives upper eight bits of an address signal and an address strobe signal, and outputs a buffered or inverted output of a buffered inverter 11 and AND gates 12a to 12d which receive a combination of outputs of the buffered inverter 11. And the AND gate 12
a NOR gate 13 for receiving the respective outputs H0 to H3 of a to 12d and generating an enable signal
When, upon receiving an AND gate 12b, and outputs H1, H3 of 12d, an OR gate 14 which generates a page number a _0, A
Upon receiving the outputs H2 and H3 of the ND gates 12c and 12d,
And a OR gate 15 for generating a page number a _1.

Further, each buffer inverter 11
The connection wiring between the AND gates 12a to 12d is configured to be programmable and changeable, so that various combinations can be realized.

Returning to FIG. 1, the mapping address input circuit 2 is a circuit for inputting a mapping address assigned to the emulation memory 5 when the target processor 6 accesses the memory. The mapping address input to the circuit 2 is provided to the connection information conversion circuit 3.

The connection information conversion circuit 3 converts the mapping address given from the mapping address input circuit 2 into information for determining a combination of inputs of the AND gates 12a to 12d shown in FIG. 2, that is, the respective buffer inverters 11 and AND gates 12a. Is converted into connection information for determining connection wirings of .about.12d. Therefore, the connection information conversion circuit 3
Generates connection information so that connection wiring of the PLD ₁ is set such that a page number (a ₀ , a ₁ ) corresponding to a given mapping address is generated. The generated connection information is provided to the PLD writing circuit 4.

According to the connection information supplied from the connection information conversion circuit 3, the PLD writing circuit 4 performs the respective buffer inverters 11 and AND gates 12 of the PLD 1.
This is a circuit for performing connection wiring (writing) of a to 12d.
When performing a write, the PLD write circuit 4 requests a bus right from the target processor 6 in advance, and performs the write after the bus right is granted. PLD writing circuit 4
For example, refer to the document “Separate volume transistor technology SP
ECIAL No. 23 P114 CQ publisher 19
90 "is a PAL writer.

In such a configuration, when the PLD 1 is programmed, for example, as shown in FIG. 2, the outputs H0 to H3 of the AND gates 12a to 12d become
Input terminals I0, I1, I2, I3, I4, I of PLD1
When 5, I6, I7, and I8 have the following combinations,
It becomes “1” level.

H0 (I0, I2, I3, I4, I5, I6, I7, I8) = (1, 1, 0, 1, 1, 1, 1, 0, 0) H1 (I0, I1, I2, I3) , I4, I5, I6, I7, I8) = (1,1,0,1,0,1,1,0,0) H2 (I0, I1, I2, I3, I4, I5, I6, I7, I8 ) = (1,0,0,0,1,0,0,1,0) H3 (I0, I1, I2, I3, I4, I5, I6, I7, I8) = (0,0,1,1) , 0, 1, 0, 1, 0) Therefore, one of the outputs H0 to H3 that outputs "1" is one. Also, the NOR gate 13
When any one of the outputs H0 to H3 becomes "1", it outputs "0" as an enable signal. The OR gate 14 outputs "1" level when the output H1 or H3 becomes "1". The gate 15 outputs "1" level when the output H2 or H3 becomes "1" level.

Here, when the upper 8 bits of the address signal become (1,1,0,1,1,1,1,0), (H0, H1, H2, H3) = (1 , 0,0,
0,), and (O0, O1, O2) = (0, 0, 0)
Is output, and the emulation memory 5 is accessed when the enable signal becomes valid. In the emulation memory 5, (a0, a1) = (0, 0)
Access is made to a memory in which a2 to ak are lower than the address signal of the target processor 6.

If none of the combinations is applicable, the emulation memory 5 is not accessed because O0 is not valid.

When the mapping address is changed, for example, the upper combination of the addresses where H0 is valid, (1,1,0,1,1,1,1,0) is (0,
1,0,1,1,1,1,0)
The internal configuration of the PLD 1 is changed by programming. Specifically, as shown in FIG. 2, the output of I0 as it is is used as the input of H0, but in order to switch this to the output of I0 inverted, the wiring at this location is changed.

Therefore, when the address at which the mapping of the emulation memory 5 is started is changed in the in-circuit emulator, the information on the address of the mapping is transferred to the connection information between each of the AND gates 12a to 12d and the buffer inverter 11. When the change is made, for example, when a part of the mapping address is changed, the connection information corresponding to the change of the wiring described above is output to the PLD 1.

As shown in FIG. 2, this mapping circuit can be constituted entirely by one PLD, and further, inside the PLD, the buffer inverter 11, AN
D gates 12a to 12d, OR / NOR gates 13 to 1
Since the output can be determined in three stages of 5, it is possible to determine the output in one stage shorter than in the prior art.

Therefore, by configuring the mapping circuit of the emulation memory in this way, it is possible to output a mapping address and an enable signal in a relatively short time.

In addition, although a plurality of combinational logic circuit elements are conventionally used, depending on the PLD, a plurality of mapping circuits can be configured with one logic circuit element. It is expected that the access time can be further reduced by reducing the size of the entire system.

[0041]

As described above, according to the present invention, the signals generated through the three-stage logic gates
Since the target processor accesses the emulation memory mapped by the mapping circuit, the target processor can access the emulation memory at a higher speed than in the past.

Also, since the mapping circuit is constituted by the buffer inverter circuit and the first to third logic gates,
The size of the mapping circuit can be reduced.

Further, since the mapped address area of the emulation memory is set in a programmable manner according to the mapping address, the mapped address area can be easily changed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an emulation system including a mapping circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing one embodiment of a PLD in the mapping circuit shown in FIG. 1;

FIG. 3 is a diagram illustrating a configuration of an emulation system including a conventional mapping circuit.

FIG. 4 is a diagram showing one conventional configuration of the mapping circuit shown in FIG. 3;

FIG. 5 is a diagram illustrating another configuration of an emulation system including a conventional mapping circuit.

FIG. 6 is a diagram showing a conventional configuration of the mapping circuit shown in FIG. 5;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 PLD 2 mapping address input circuit 3 connection information conversion circuit 4 PLD write circuit 5 emulation memory 6 target processor 11 buffer inverters 12 a to 12 d AND gate 13 NOR gate 14, 15 OR gate

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 11/22

Claims (2)

(57) [Claims] 1. A plurality of buffer inverter circuits for receiving an address given from a target processor and for buffering or inverting the address, and for receiving the buffer output or inverting output of the buffer inverter circuit and receiving the buffer output or inversion. A plurality of first logic gates for performing a logical operation on an output, and a second logic for receiving and outputting the first logic gate to generate and output a first selection signal for selecting an emulation memory and making it accessible. A gate, receiving an output of the first logic gate, and selecting an address area of the emulation memory set in advance corresponding to a mapping address mapped to the emulation memory from addresses given by the target processor A third selection signal for generating and outputting a second selection signal to be designated A logic gate, wherein a combination of a buffer output or an inverted output of the buffer inverter circuit provided to the first logic gate is programmably changed.
And for a memory access of the target processor,
When changing the mapping address mapped to the emulation memory, an input circuit for inputting a mapping address newly mapped to the emulation memory; and a mapping address given from the input circuit to the first logic gate. A conversion circuit for converting connection information to determine a combination of an output of the buffer inverter circuit or an inverted output to be provided, and according to the connection information obtained by the conversion circuit,
P for changing the combination of the output or inverted output of the buffer inverter circuit applied to the first logic gate
An emulation memory mapping circuit, comprising: an LD writing circuit. 2. A target processor for accessing a memory by outputting an address by executing a program, an emulation memory acting on behalf of a memory accessed by the target processor, and a mapping circuit according to claim 1. Emulation system.