KR100236530B1 - Address generating circuit of a digital signal processor - Google Patents

Abstract

The present invention discloses an address generating circuit of a digital signal processing apparatus. The circuit includes a plurality of first registers for storing a first bank address pointer value, a plurality of second registers for storing a second bank address pointer value, and the plurality of first registers in response to a decoding signal of first control bit data. A plurality of first switching means for transmitting an output signal of a register selected from among the first registers, a first latch, and second control bit data for storing an address selected by the plurality of first switching means A plurality of second switching means for transmitting an output signal of a selected one of the plurality of second registers in response to a decoded signal of the second register, a second for storing an address selected by the plurality of second switching means Inputting each of the plurality of first and second registers by adding an output signal of a second latch and the first and second latches; And third switching means for transmitting the output signal of the first latch or the output signal of the second latch to the address bus in response to the mode selection data. Therefore, the number of address pointers can be increased by adding a minimum of hardware, so that an increase in chip area at the time of integration can be prevented.

Description

Address generation circuit of digital signal processing device

The present invention relates to a digital signal processing apparatus, and more particularly, to an address generating circuit of a digital signal processing apparatus for memory access in the digital signal processing apparatus.

Digital signal processors basically have a memory-based structure. Therefore, in order to implement various digital signal processing algorithms, instructions that read or write input data, coefficients, and output data from memory are an important part and occur very frequently. Therefore, the configuration of the address generator for generating an address for memory access is one of the important factors that influence the performance of the digital signal processing apparatus.

The logic that occupies most of the address generator is adders and registers for indirect addressing. Indirect addressing is an addressing method that puts the value of the selected address pointer register on the address bus and sends the address to memory, adds the address with the value of the index register, and updates the address to be accessed next to the address pointer. This is very useful when reading data sequentially in implementing a filter. In this case, the address pointer stores initial data of a memory data segment to be accessed and an index register stores a modifier value. For example, to sequentially access a value in one memory data segment, "1" may be stored in the modifier. In the case of sequentially accessing a double precision value, "2" may be stored in the modifier.

Indirect addressing also allows indexed addressing, which stores the base address value of each data memory segment in an address pointer and inserts an index value into an index register to access specific data in the segment.

The important thing in this indirect addressing is how many address pointers and how many index registers to put. This is because the optimal number of address pointers and the number of index registers is highly algorithm dependent. In algorithms that require multiple memory segments, the number of address pointers is the dominant factor, and if irregular memory accesses are required within one segment, the number of index registers is the dominant factor.

A general-purpose digital signal processing device is a programmable device and should be applicable to various applications, not just for any particular application. If the hardware is fixed by a certain number of address pointers and index registers, it may not operate efficiently in some applications.

Fig. 1 is a block diagram of an address generating circuit of a conventional digital signal processing apparatus, which shows an address generating circuit having two address pointers and four indexes. The address generating circuit of Fig. 1 includes address pointer registers 10 and 12 for designating an address pointer, index registers 14, 16, 18 and 20 for storing an index value, and input buffers 34 and 36. , Adder 40, and tri-state buffers 22, 24, 26, 28, 30, 32, 38 for passage control. Then, for the address generating circuit shown in Fig. 1, 1 bit for selecting two address pointers and 2 bits for selecting one of four index values are respectively decoded in the 16-bit instruction register used in the 16-bit digital signal processing apparatus. To control the tri-state latches 22, 24 and 26, 28, 30, 32. In FIG. 1, the output signal of the adder 40 is fed back to the address pointer registers 10 and 12 so that the address pointer is updated. That is, when the indirect addressing instruction is executed, the value of the address pointer selected in the instruction is sent to the address bus, and then the address pointer is updated by adding the value of the index register selected in the instruction to the address pointer register.

The above-described address generation circuit of the conventional digital signal processing apparatus can use only addressing using up to two address pointers at a time, and the index register stores only modifier values added to the address pointers. Therefore, if more than three data segments are required in the case of having two address pointers and four index registers, the existing address pointer values must be stored in a memory device or elsewhere, and the required address pointer values must be moved. There is a problem that the cycle is increased when is changed to cause a decrease in performance.

In order to solve the above problems, one of the methods used in the conventional digital signal processing apparatus uses the concept of a shadow register to execute an active register bank by executing a specific instruction with an alternate register corresponding to each address pointer. By swapping or assigning a specific bit to a status register indicating the status of the processor, the mode is changed so that the address pointer of the alternate bank can be used at a particular point in time. However, this method has a problem of adding a large hardware such as a register.

An object of the present invention is to provide an address generating circuit of a digital signal processing apparatus that can adjust the number of address pointers and index values with the addition of a minimum of hardware.

The address generating circuit of the digital signal processing apparatus of the present invention for achieving the above object includes a plurality of first registers for storing a first bank address pointer value and a plurality of second registers for storing a second bank address pointer value. Registers, a plurality of first switching means for transmitting an output signal of a selected one of the plurality of first registers in response to the decoding signal of the first control bit data, the plurality of first switching means A plurality of second switching means for transmitting an output signal of a register selected from the plurality of second registers in response to a first latch for storing an address selected by the second control bit data; A second latch, said first latch and a second latch for storing an address selected by a plurality of second switching means Addition means for adding the output signals of the first and second registers to each of the plurality of first and second registers, and transmitting the output signal of the first latch or the output signal of the second latch to an address bus in response to mode selection data. It is characterized by having a third switching means for.

1 is a block diagram of an address generating circuit of a conventional digital signal processing apparatus.

2 is a block diagram of an address generating circuit of the digital signal processing apparatus of the present invention.

3 is a logic circuit diagram of a control circuit for controlling the circuit shown in FIG.

Hereinafter, an address generating circuit of the digital signal processing apparatus of the present invention will be described with reference to the accompanying drawings.

Fig. 2 is a block diagram of an address generating circuit of the digital signal processing apparatus of the present invention, which shows an address generating circuit having two address pointers and four index values. The address generation circuit shown in Fig. 2 includes bank 0 address pointer registers 10 and 12, bank 1 address pointer registers 14, 16, 18 and 20, input latches 34 and 36, adder 40, And three-state buffers 22, 24, 26, 28, 30, 32, 38, and 42 for passage control. The circuit shown in Fig. 2 is configured such that the output signal of the adder 40 is fed back not only to the conventional address pointer registers but also to the index registers. It is different from the circuit configuration shown in Fig. 1 that the control 3-state buffer 42 is also output to the address bus.

In this configuration, not only the bank 0 address pointer but also the bank 1 address pointer can be used as the address pointer, so that it can have six address pointers. At this point, it may have either address pointers stored in the two address pointer registers 10, 12 or address pointers stored in the four address pointer registers 14, 16, 18, 20.

In order to control the operation of the circuit shown in FIG. 2, since the register select bit 1 bit for bank 0 and the register select bit 2 bit for bank 1 are required, the instruction set can be used as it is without changing the conventional instruction form. 1 bit for the address mode is allocated to a register indicating a state of the digital signal processing apparatus such as a status register. When the bit is "0", bank 0 is indicated as an address pointer as shown in FIG. Bank 1 can be used as an index register. If "1", bank 1 can be used as an address pointer and bank 0 can be used as an index register. Therefore, the user can select the mode according to the characteristics of the system application to create an application program, or sometimes perform the addressing while changing the mode as needed in one application.

3 is a logic circuit diagram of a control circuit for controlling the circuit shown in FIG. 2, which includes an instruction register 50, a status register 60, inverters 70, 72, 74, 76, 78, 100, and an AND gate. Field 80, 82, 84, 86, 88, 90, 92, 94, 96, 98.

If the control bit of the status register 60 is "0", the value of the bank 0 register is used as the address pointer and the value of the bank 1 register is used as the index value. The value of this control bit causes the tri-state buffer 38 of FIG. 2 to conduct so that the value of the latch 34 is output to the address bus. At this time, if the bank 0 selection control bit of the instruction register 50 is "0", the buffer 24 is turned on, and if the output signal of the register 12 is latched to the latch 34, and the buffer 22 is "1", And the output signal of the register 10 is latched to the latch 34. In addition, when the bank1 selection control bit is "0", the output signal of the AND gate 86 becomes "1" and the buffer 32 is turned on so that the latch 36 latches the output signal of the bank1 register 20. Is latched 34). If the control bit is "1", the register 18 is latched, if the control bit is "10", the register 16 is latched, and if the control bit is "11", the output signal of the register 14 is latched to the latch 34, respectively.

If the value of the status register 60 is "1", the value of the bank 0 register is used as the index value, the value of the bank 1 register is used as the address pointer, and the value of the mode control bit is conducted to the buffer 42 of FIG. The latch 36 is then output to the address bus. The selection of the register according to the data of the bank 0 selection control bit and the bank 1 selection control bit is the same as described above.

In the above-described embodiment, only the address generating circuit which can have two address pointers or four address pointers is described, but the number of address pointers of the banks can be adjusted by adjusting the bank select bit of the instruction register, and the number of bits of the status register. By increasing the number and increasing the number of control banks in the instruction register, more various addresses can be generated.

Therefore, the address generating circuit of the digital signal processing apparatus of the present invention can increase the number of address pointers with the addition of a minimum of hardware, thereby preventing an increase in chip area during integration.

Claims (3)

A plurality of first registers for storing a first bank address pointer value; A plurality of second registers for storing a second bank address pointer value; A plurality of first switching means for transmitting an output signal of a selected one of the plurality of first registers in response to the decoding signal of the first control bit data; A first latch for storing an address selected by the plurality of first switching means; A plurality of second switching means for transmitting an output signal of a selected one of the plurality of second registers in response to the decoding signal of the second control bit data; A second latch for storing an address selected by the plurality of second switching means; Adding means for adding the first and second latch output signals to each of the plurality of first and second registers to increase the number of address pointers; And third switching means for transmitting the output signal of the first latch or the output signal of the second latch to an address bus in response to mode selection data. The address generating circuit of claim 1, wherein the first and second control bit data are stored in an instruction register. The address generation circuit of a digital signal processing apparatus according to claim 1, wherein said mode selection data is stored in a status register.

Images