JPS6255752A - Control system for extension of data bus - Google Patents

Abstract

PURPOSE:To reduce the delay of the data signal and also to prevent the effects of noises by providing an exchange buffer between high-order and low-order sides of a data bus not only at the main body side but at the extended point of the data bus and therefore reducing the transfer route of data in the case of the DMA transfer of half data width. CONSTITUTION:When data are transferred to an I/O 36 from a memory 35, the direction 19 of an high-order data buffer is set toward the main body from an extended point of a data bus since a memory lead 17, a bus high enable signal 26 and an extended memory enable signal 31 are effective. The signal 26 and a DMA enable signal 30 are effective and a word 28 is ineffective. Thus an exchange buffer enable signal 18 set exchange buffers 7 and 8 under enable states. Here the lead 17 is effective and receives data at the lower side. Thus a low-order data buffer enable signal 24 of an extended point sets a lower data buffer in a disenable state.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a data bus extension control method when extending a data bus, and particularly relates to a data bus extension control method when extending a data bus, and in particular, a data bus with half the data width of the entire data bus (for example, 8 bit width in a 16 bit system). DMA of
This invention relates to a data bus control method when performing transfer.

[Conventional technology]

Conventionally, when a data bus is extended and a memory or input/output device (hereinafter referred to as I/Q) is connected to the extended data bus, the data bus control circuit has a configuration as shown in FIG.

That is, upper data buffers 3 and 4 are controlled by upper data buffer direction 19 and upper data buffer enable 21, and lower data buffers 5 and 6 are controlled by lower data buffer direction 20 and lower data buffer enable 22. The direction and enable/disable of each buffer are controlled. Further, the direction and enable/disable of the exchange buffer 7 are controlled by a memory read 17 and an exchange buffer enable 18, which are signals serving as directions thereof.

The buffer control circuit 9 determines how to control the upper data buffers 3 and 4, the lower data buffers 15 and 6, and the exchange buffer 7 using 11 types of control signals described below, and sets the exchange buffer enable 18 . Upper data buffer directory 19. Lower data buffer directory 20. Upper data buffer enable 2L generates lower data buffer enable 22.

The memory read 17 and the work 10 read 25 are control signals from the CPU or the DMA controller, and indicate that data is read from the memory and data is read from the work 10, respectively. Pass high enable 26 is a signal that allows data to exist on the upper half of the data bus. The pass row enable 27 is a signal that allows data to exist in the lower half of the data bus, but generally the lowest address signal is used in negative logic. Word 28 is a signal indicating that the data transfer width is the entire data bus width. The CPU enable 29 is a signal indicating that the CPU is using the data bus, and the DMA enable 30 is a signal indicating that the data bus is transferring DMA. The extension destination memory enable 31 is a signal indicating that the memory connected to the extension destination path is selected, and is obtained by decoding the address of the extension destination memory. The extension destination DMA acknowledge 32 is a signal indicating that the DMA of the DMA request from the device at the extension destination of the path is being transferred. Obtained from the signal indicating that it is inside. Extension destination bus high valid 33 and extension destination bus low valid 34 are signals indicating that data actually exists on the extension destination data bus, and are negative logic 0R (NAND) of the extension destination data bus. It can be obtained by taking . Note that in the case of data in which all bits are 1, it is treated as if the data does not exist, but there is no problem because the state of the data bus is the same as when no data exists.

Based on the above explanation of the control signals, the buffer control circuit 9
An example of control will be explained.

Normally, the upper data buffer direction 19. The lower data buffer direction 20 is controlled, and the upper data buffer direction 19. Lower data buffer direction 2
0 is controlled.

The upper data buffer direction 19 is activated when the memory read 17, path high enable 26, and extension destination memory enable 31 are valid, or when the I/Q read 25, word 28, and extension destination DMA acknowledge 32 are enabled.
is enabled, or I10 lead 25 and pass high
Enable 26, CPU enable 29, and extension destination path.
High valid 33 is valid, and lower data buffer direction 20 is valid when memory read 17, path row enable 27, and extension destination memory enable 31 are valid, or When the destination DMA acknowledge 32 is valid, or when the I10 read 25, pass row enable 27, CPU enable 29, and destination bus low valid 34 are valid, the data bus is transferred from the destination to the main body. Make sure it is facing the same direction.

The upper data buffer enable 21 is used by the upper data buffer direction 19 and also by the lower data buffer direction.
Enable 22 is the lower data pad directory blind 2
When a 0 inverts, it temporarily disables the data buffer and enables the others to avoid data collisions on the data bus.

Exchange buffer enable 18 is set to word 28 with pass high enable 26 and DMA enable 30 enabled.
is disabled, the exchange buffer 7 is enabled, and the others are disabled.

FIG. 5 shows DMA transfer of the full data bus width.

If memory read and write 10, memory read 1
7 and pass high enable/I/26 and extended memory
Enable 31 is enabled, and the upper data buffer
Direction declaration 19 is set so that the data bus is directed from the extension destination to the main body.
047''-Tanocus is controlled so that it faces from the extension to the main body.

In the case of a transfer from a lower-level memory to Ilo with half the data width shown in Fig. 6, ``memory read 17 and path
Since the row enable/I/27 and the extension destination memory enable 31 are enabled, the lower data buffer directory 20 is controlled so that the data node is directed from the extension destination to the main body.

In the case of transfer from the memory connected to the upper level in FIG. The silane 19 is controlled so that the data bus is oriented from the extension to the main body. Exchange buffer enable 18 also enables exchange buffer 7 since pass high enable 26 and DMA enable 30 are valid and word 28 is invalid.

DMA transfer between devices connected to the extension destination of the above-mentioned data bus will be further explained.

First, in the case of the full data bus width, control is performed as shown in FIG. 5, and the exchange buffer 7 is not required. However, in the case of DMA transfer with a data width that is half of the total data bus, generally
0 data bus, and it is necessary to perform transfer alternately between the memories connected to the lower part of the data bus and the memories connected to the upper part of the data bus.

FIG. 6 is a diagram of transfer from a memory connected to a lower level to Ilo, and FIG. 7 is a diagram of transfer from a memory connected to an upper level to Ilo. In the case of FIG. 7, since the exchange buffer 7 is required, the transfer data passes through the extended upper data bus 12 and lower data bus 15.

[Problem that the invention seeks to solve]

In the conventional method described above, when performing DMA transfer of half the data width of the entire data bus between devices connected to the extended end of the data bus, an exchange buffer is required, so the transferred data is extended. The data bus will be reciprocated on the data bus.

Therefore, in this case, there are problems in that the data transfer path is longer than that of CPU transfer or DMA transfer of the full data bus width, signal delay is increased, and noise is more likely to occur.

[Means for solving problems]

The method of the present invention is a data bus extension control method for performing direct memory access with a data width that is 1/2 of the data width of the data bus in a data bus extension circuit. a data exchange buffer for exchanging data between the partial data bus and a second partial data bus consisting of 1/2 of the width; a first data buffer provided on the first partial data bus; a second data buffer provided on a second partial data bus, and when the data exchange buffer 1 is activated, at least one of the first data buffer and the second data buffer is inactivated; and a control means.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The data bus extension control method shown in FIG. 1 adds an exchange buffer 18 and an extension destination data buffer enable control circuit 10 to the conventional method shown in FIG.
An enable 23 and an extended optical lower data buffer enable 24 are provided separately from the upper data buffer enable 21 and the lower data buffer directories 22.

The exchange buffer 8 is controlled in the same way as the conventional exchange buffer 7.

The extended optical data buffer enable control circuit 10 includes an upper data buffer enable 21. Lower data pad enable 22. Memory read 17. Exchange buffer/
Enter enable 18.

The extension destination upper data buffer enable 23 and the extension optical lower data buffer enable 24 are used when the upper data buffer enable 21 and the lower data buffer enable 22 disable the upper data buffer 3 and the lower data buffer 5, respectively. Similarly, the upper data buffer 14 and the lower data buffer 6, which are the extension destinations, are disabled. Also, exchange buffer enable 1
8 enables exchange buffers 17 and 8;
The memory read 17 determines whether the upper or lower side is the side that receives the data, and connects the memory connected to the upper data bus to which the upper data buffer 14 or the lower data is extended on the data receiving side and the lower data bus. Il that was done
DMA transfer to and from o will be explained.

In the transfer from the memory 35 to the Ilo 36 in FIG. Orient the bus from the extension to the main body.

Also, bus high enable 26 and DMA enable 3
0 is valid and word 28 is invalid, exchange buffer enable 18 enables exchange buffer 7.8. At this time, the memory read 17 is valid and the lower side is on the data receiving side, so the extension light lower data buffer enable 24 disables the lower data buffer 6.

In the transfer from the Ilo 36 to the memory 35 in FIG. direction.

Also, bus high enable 26 and DMA enable 3
0 is valid and word 28 is invalid, exchange buffer enable 18 enables exchange buffer 7.8. At this time, the memory read 17 is invalid and the upper end is the data receiving side, so the extended upper end data buffer enable 23 disables the upper end data buffer 4. Therefore, the data transfer route is a route passing through the exchange buffer 8 in the extended data bus control circuit 2.

In this way, in this embodiment, the memory connected to the upper data bus of the extension destination and the Ilo connected to the lower data bus
It is possible to prevent transfer delays and interference due to noise during DMA transfer between the two devices.

〔Effect of the invention〕

As explained above, the present invention provides an exchange buffer between the upper and lower parts of the data bus not only on the main body side but also at the extension destination of the bus, so that all data between devices connected to the extension destination of the bus can be exchanged. In the case of DMA transfer with a data width that is half the width of the bus, the data transfer path can be shortened.

This has the advantage that, compared to conventional systems, delays in data signals due to bus extension can be reduced, the effects of noise can also be prevented, and the data bus can be extended longer.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 and 3 show the memory connected to the upper data bus that has been extended in the configuration of FIG. DM with half data width between Ilo connected to lower data bus
FIG. 4 is a block diagram showing the conventional method; FIGS. FIG. 6 is a diagram showing the states of data buffers and exchange buffers, and data paths when performing DMA transfer between devices connected to the extension destination of the bus in the configuration shown in the figure.

Claims (1)

[Claims] In the data bus extension circuit, one of the data width of the data bus
In a data bus extension control method for direct memory access with a data width of /2, a first partial data bus consisting of 1/2 of the data bus and a second partial data bus consisting of 1/2 of the remaining data bus. a data exchange buffer for exchanging data between; a first data buffer provided on the first partial data bus; and a second data buffer provided on the second partial data bus; A data bus extension control system comprising: control means for disabling at least one of the first data buffer and the second data buffer when the data exchange buffer is activated.