JPH0221866U - - Google Patents
Info
- Publication number
- JPH0221866U JPH0221866U JP5338688U JP5338688U JPH0221866U JP H0221866 U JPH0221866 U JP H0221866U JP 5338688 U JP5338688 U JP 5338688U JP 5338688 U JP5338688 U JP 5338688U JP H0221866 U JPH0221866 U JP H0221866U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- filter
- period
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Picture Signal Circuits (AREA)
- Filters That Use Time-Delay Elements (AREA)
Description
第１図は本願の第１の考案の実施例を示すブロ
ツク図、第２図はその各部の信号波形図、第３図
は本願の第２の考案の一実施例を示すブロツク図
、第４図はその各部の信号波形図、第５図は本願
の第２の考案の他の実施例を示すブロツク図、第
６図は従来の１次元フイルタ回路の一例を示すブ
ロツク図、第７図は従来の２次元フイルタ回路の
一例を示すブロツク図、第８図は第１図のフイル
タ回路部のインパルス応答を示す図である。
２１〜２４：単位遅延回路、３０〜３４：係数
乗算器、４：加算器、６：１次元フイルタ回路、
７，２２：切換回路、８：同期信号期間検出回路
、９：切換信号発生回路、１１，１８：エツジ部
サンプルホールド回路。
FIG. 1 is a block diagram showing an embodiment of the first invention of the present application, FIG. 2 is a signal waveform diagram of each part thereof, FIG. 3 is a block diagram showing an embodiment of the second invention of the present application, and FIG. 5 is a block diagram showing another embodiment of the second invention of the present application. FIG. 6 is a block diagram showing an example of a conventional one-dimensional filter circuit. FIG. 7 is a block diagram showing an example of a conventional one-dimensional filter circuit. A block diagram showing an example of a conventional two-dimensional filter circuit, FIG. 8 is a diagram showing an impulse response of the filter circuit section of FIG. 1. 21 to 24 : unit delay circuit, 30 to 34: coefficient multiplier, 4 : adder, 6: one-dimensional filter circuit,
7, 22: switching circuit, 8: synchronizing signal period detection circuit, 9: switching signal generation circuit, 11, 18: edge section sample and hold circuit.
Claims (1)
得る信号をそれぞれ重み付けして累積加算し出力
するフイルタ部と、このフイルタ部での遅延時間
に相当する時間だけ前記映像信号を遅延せしめる
遅延回路と、前記フイルタ部から前記同期信号期
間を除く映像信号期間の信号のみに基づく出力信
号が現われている期間を示す切換信号を作成する
回路と、この切換信号の期間のみ前記フイルタ部
の出力信号を導出しそれ以外の期間では前記遅延
回路の出力信号を導出する切換回路とを備え、こ
の切換回路の出力信号をフイルタ出力とするよう
にした映像信号処理用フイルタ回路。 (2) 入力映像信号を単位時間づつ順次遅延して
得る信号をそれぞれ重み付けして累積加算し出力
するフイルタ部と、このフイルタ部での遅延時間
に相当する時間だけ前記映像信号を遅延せしめる
遅延回路と、前記映像信号の同期信号に隣接する
各エツジ部のレベルをサンプルホールドする回路
と、前記遅延回路の出力信号中の映像信号期間の
前後にそれぞれ位置し前記遅延時間に相当するパ
ルス幅をもつ切換信号を作成する回路と、この切
換信号のパルス期間のみ前記サンプルホールド回
路の出力信号を上記フイルタ部に入力しそれ以外
の期間では前記遅延回路の出力信号を上記フイル
タ部に入力せしめる切換回路とを備え、前記フイ
ルタ部から出力信号を導出するようにした映像信
号処理用フイルタ回路。[Claims for Utility Model Registration] (1) A filter unit that weights and cumulatively adds signals obtained by sequentially delaying input video signals by unit time and outputs the signals, and only the time corresponding to the delay time in this filter unit. a delay circuit for delaying the video signal; a circuit for creating a switching signal indicating a period during which an output signal based only on a signal of the video signal period excluding the synchronizing signal period from the filter section appears; and a period of the switching signal. A video signal processing filter circuit comprising a switching circuit for deriving the output signal of the filter section only during the period and deriving the output signal of the delay circuit for the other periods, and the output signal of the switching circuit is used as the filter output. . (2) A filter unit that weights and cumulatively adds signals obtained by sequentially delaying an input video signal by unit time, and outputs the resultant signals, and a delay circuit that delays the video signal by a time corresponding to the delay time in this filter unit. a circuit that samples and holds the level of each edge portion adjacent to the synchronization signal of the video signal; and a circuit that is located before and after the video signal period in the output signal of the delay circuit and has a pulse width corresponding to the delay time. a circuit for creating a switching signal; and a switching circuit for inputting the output signal of the sample and hold circuit to the filter section only during the pulse period of the switching signal, and inputting the output signal of the delay circuit to the filter section for other periods. A filter circuit for video signal processing, comprising: a filter circuit for deriving an output signal from the filter section.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5338688U JPH0733491Y2 (en) | 1987-12-18 | 1988-04-20 | Video signal processing filter circuit |
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19319887 | 1987-12-18 | ||
| JP63-34327 | 1988-03-14 | ||
| JP3432788 | 1988-03-14 | ||
| JP62-193198 | 1988-03-14 | ||
| JP5338688U JPH0733491Y2 (en) | 1987-12-18 | 1988-04-20 | Video signal processing filter circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0221866U true JPH0221866U (en) | 1990-02-14 |
| JPH0733491Y2 JPH0733491Y2 (en) | 1995-07-31 |
Family
ID=31721128
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5338688U Expired - Lifetime JPH0733491Y2 (en) | 1987-12-18 | 1988-04-20 | Video signal processing filter circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0733491Y2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006048981A1 (en) * | 2004-11-01 | 2006-05-11 | Niigata Seimitsu Co., Ltd. | Image processor |
-
1988
- 1988-04-20 JP JP5338688U patent/JPH0733491Y2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2006048981A1 (en) * | 2004-11-01 | 2006-05-11 | Niigata Seimitsu Co., Ltd. | Image processor |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0733491Y2 (en) | 1995-07-31 |
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