JPS55104153A - Suppressor for pulsive noise - Google Patents

Suppressor for pulsive noise

Info

Publication number
JPS55104153A
JPS55104153A JP1167179A JP1167179A JPS55104153A JP S55104153 A JPS55104153 A JP S55104153A JP 1167179 A JP1167179 A JP 1167179A JP 1167179 A JP1167179 A JP 1167179A JP S55104153 A JPS55104153 A JP S55104153A
Authority
JP
Japan
Prior art keywords
signal
noise
switch
delay circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1167179A
Other languages
Japanese (ja)
Other versions
JPS5946458B2 (en
Inventor
Masahiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP1167179A priority Critical patent/JPS5946458B2/en
Publication of JPS55104153A publication Critical patent/JPS55104153A/en
Publication of JPS5946458B2 publication Critical patent/JPS5946458B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To enable to perform accurate interpolation, by synthesizing the interpolation signal from the signal advanced and delayed of the time phase for an integer multiple of the pilot signal period while pulsive noise is superimposed on the stereo composite signal.
CONSTITUTION: The input signal from the FM detection circuit is fed to the noise detection circuit 2 via the high pass filter 1 and noise is detected. This detection signal drives the monostable multivibrator 3 and the signal to drive the switches 6 and 10 is formed with the delay circuit 4 and the gate 12. Immediately before the noise pulse is fed to the switch 6 from the first delay circuit 7 with the switch 6, the selection is made to the output of the second delay circuit 8 to avoid the noise pulse. Further, the switch 10 selects the sum circuit 9 and the switch 6 for the output, and the waveform interpolation during the suppression of pulsive noise performs noise suppression at the average signal between the delayed signal and advanced signal for the phase in MTP from the signal suppressed. Where M is an integer and TP is the pilot signal period in the stereo composite signal.
COPYRIGHT: (C)1980,JPO&Japio
JP1167179A 1979-02-02 1979-02-02 Pulse noise suppression device Expired JPS5946458B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1167179A JPS5946458B2 (en) 1979-02-02 1979-02-02 Pulse noise suppression device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1167179A JPS5946458B2 (en) 1979-02-02 1979-02-02 Pulse noise suppression device

Publications (2)

Publication Number Publication Date
JPS55104153A true JPS55104153A (en) 1980-08-09
JPS5946458B2 JPS5946458B2 (en) 1984-11-13

Family

ID=11784440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1167179A Expired JPS5946458B2 (en) 1979-02-02 1979-02-02 Pulse noise suppression device

Country Status (1)

Country Link
JP (1) JPS5946458B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS622294U (en) * 1985-06-19 1987-01-08

Also Published As

Publication number Publication date
JPS5946458B2 (en) 1984-11-13

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