JPS5526720A - Noise pulse suppression system - Google Patents

Noise pulse suppression system

Info

Publication number
JPS5526720A
JPS5526720A JP9921678A JP9921678A JPS5526720A JP S5526720 A JPS5526720 A JP S5526720A JP 9921678 A JP9921678 A JP 9921678A JP 9921678 A JP9921678 A JP 9921678A JP S5526720 A JPS5526720 A JP S5526720A
Authority
JP
Japan
Prior art keywords
signal
delay
noise pulse
output
interpolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9921678A
Other languages
Japanese (ja)
Inventor
Masahiro Watanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP9921678A priority Critical patent/JPS5526720A/en
Publication of JPS5526720A publication Critical patent/JPS5526720A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform more accurately the interpolation of a composite signal waveform in noise pulse compression by using a sum signal of a memory signal and delay input as an interpolation signal for a constant time as a substitute for a delay output.
CONSTITUTION: Output S(t) of a frequency discriminator circuit is delayed 1 by a fixed period of time to obtain its delay input-output difference 5, the difference signal of it is stored 6 for a constant time starting immediately before the leading edge of a noise pulse appears in the delay output, and the sum signal of the signal of memory circuit 6 and the input of delay circuit 1 is substituted as an interpolation signal for the delay output for the fixed time. Consequently, a composite signal waveform can be interpolated in noise pulse compression more accurately.
COPYRIGHT: (C)1980,JPO&Japio
JP9921678A 1978-08-14 1978-08-14 Noise pulse suppression system Pending JPS5526720A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9921678A JPS5526720A (en) 1978-08-14 1978-08-14 Noise pulse suppression system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9921678A JPS5526720A (en) 1978-08-14 1978-08-14 Noise pulse suppression system

Publications (1)

Publication Number Publication Date
JPS5526720A true JPS5526720A (en) 1980-02-26

Family

ID=14241453

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9921678A Pending JPS5526720A (en) 1978-08-14 1978-08-14 Noise pulse suppression system

Country Status (1)

Country Link
JP (1) JPS5526720A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0199316A (en) * 1987-10-13 1989-04-18 Sanyo Electric Co Ltd Pulsative noise eliminating device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0199316A (en) * 1987-10-13 1989-04-18 Sanyo Electric Co Ltd Pulsative noise eliminating device

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