JPH02271733A - Phase detection circuit - Google Patents

Abstract

PURPOSE:To decrease the circuit scale by squaring a sampled input signal, generating a difference signal between the squared signal and a signal resulting from retarding the squared signal by a half period of the timing component and accumulating the difference signal and outputting it. CONSTITUTION:An input signal is sampled in the timing of a clock signal and the result is fed to a multiplier 1. The multiplier 1 squares an input signal and gives the result to one input terminal of a subtractor 3, the signal is retarded by a half the clock period T of the input signal at a delay device 2 and given to the other input terminal of the subtractor 3. A difference signal sent from the subtractor 3 is sampled at an interval of the clock period T of the input signal to a switch SW2 and fed to an adder 4. A multiplier 5 multiplies a constant (a) smaller than 1 with a transmission signal from the adder 4, which adds and outputs the signal resulting from the input signal retarded by the period T of the clock at a delay device 6 to the signal from the switch SW2. Thus, the increase and divergence of the result of accumulation is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a phase detection circuit, and particularly to a phase detection circuit for detecting an optimum sampling phase on the receiving side of a digital communication system or the like.

[Conventional technology]

Conventionally, this type of phase detection circuit has been designed to sample a signal received via a transmission line at the timing of the clock signal to be phase detected, which is synchronized in frequency with the timing clock, and to sample the signal received via a transmission line by half a clock period. Both sampling results, including those sampled at different timings, are passed through a non-linear circuit such as a squaring circuit, and the differences between the two are cumulatively added to determine whether the phase of the clock signal to be detected is from the optimal sampling phase. The so-called wave difference method (Wave Difference Method) is used to send out a phase error signal that indicates how much the difference is.
od, abbreviated as WD method. For example, IEEE Tra-n
actions on communication
s, C0M-33, No. 6, “Timin
gRecovery in Dig-ital 5
ubscriber Loops” (author, 0.A
gazzi et al.). ) is applied.

FIG. 2 is a block diagram of a conventional phase detection circuit to which the above-mentioned WD method is applied. The input signal is a received signal via a transmission path, the clock signal (1) is a signal whose phase is to be detected, and the clock signal (2) is a signal obtained by shifting clock signal (1) by half a clock period (T/2). .

The switches SW3 and SW4 are for sampling the input signal, and sample the input signal at the timing of the clock signals (1) and (2), respectively, and send it to the multiplier 1. The two multipliers 1 each square the sampled value of the input signal and send it to the adder 4.

The adder 4 delays its own output signal by one clock cycle (T) using the delay device 6 and adds it to the output signal of the multiplier 1 to obtain the cumulative sum of the output values of the multiplier 1. Send the signal to subtractor 3. The subtracter 3 sends out a difference signal between the signals sent out by the two adders 4, and the switch SW2 samples and outputs this difference signal every clock cycle (T).

The resulting output signal will be zero if the phase of the clock signal (1) is the optimal sampling phase, and its absolute value will increase as it deviates from the optimal phase, indicating a phase error.

[Problem to be solved by the invention]

The conventional phase detection circuit described above has two sampling switches, two squaring circuits, and two cumulative addition circuits each, and has a problem in that the circuit scale becomes large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a phase detection circuit that solves the above-mentioned problems and has a smaller circuit scale than the conventional one.

[Means to solve the problem]

The circuit of the present invention includes a sampling means for sampling an input signal including a timing component with a predetermined period at the timing of a clock signal having a period half the period of the timing component, and a circuit that squares the sampled input signal. a subtracting means for generating a difference signal between the squared signal and a signal delayed by a half period of the previous timing component; and a subtraction means for cumulatively adding the difference signal for each period of the timing component. and cumulative addition means for outputting.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The input signal is a received signal from the transmission path, and the clock signal is a signal whose phase is to be detected and has a clock rate twice that of the received signal. The switch SW1 is for sampling the input signal, samples the input signal at the timing of the clock signal, and sends it to the multiplier 1 for squaring. Multiplier 1 squares the sampled input signal and directly sends it to one input terminal of subtracter 3, and also delays it by half a clock period (T/2) of the input signal in delay device 2. , subtractor 3
Send it to the other input end of the . The difference signal sent out by the subtracter 3 is output by the switch SWz, and the input signal is divided into four cycles (T).
After being sampled every other time, it is sent to an adder 4 for cumulative addition. Adder 4 adds 1 to its own sending signal with multiplier 5.
After being multiplied by a constant a that is slightly smaller than , the input signal delayed by one clock period (T) in the delay device 6 is added to the signal coming from the switch SW2, and the addition result is output. Note that the reason why the constant a is multiplied during the cumulative addition loop is to prevent the cumulative addition result from increasing and diverging.

In this embodiment, by sampling the input signal at intervals of half a period (T/2) of its clock timing,
The input sampling switch, squaring circuit, and cumulative addition circuit, which are used in two units in the conventional circuit, can be time-divided and reduced to one, and the same arithmetic processing results as in the conventional circuit can be obtained.

〔Effect of the invention〕

As explained above, according to the present invention, the circuit scale can be made smaller than the conventional circuit.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional phase detection circuit. 1.5... Multiplier, 2,6... Delay device, 3... Subtractor, 4... Adder, SW
1~SW4...Switch. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] sampling means for sampling an input signal including a timing component with a predetermined period at the timing of a block signal having a period half the period of the timing component;
a multiplication means for squaring the sampled input signal; a subtraction means for generating a difference signal between the squared signal and a signal delayed by a half period of the previous timing component; 1. A phase detection circuit comprising: cumulative addition means for cumulatively adding and outputting the cumulative addition for each cycle of components.