KR970055557A - Signal phase detection device - Google Patents

Signal phase detection device Download PDF

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Publication number
KR970055557A
KR970055557A KR1019950061453A KR19950061453A KR970055557A KR 970055557 A KR970055557 A KR 970055557A KR 1019950061453 A KR1019950061453 A KR 1019950061453A KR 19950061453 A KR19950061453 A KR 19950061453A KR 970055557 A KR970055557 A KR 970055557A
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KR
South Korea
Prior art keywords
phase
signal
phase delay
detection device
lag
Prior art date
Application number
KR1019950061453A
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Korean (ko)
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KR0170524B1 (en
Inventor
성영철
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정장호
Lg 정보통신주식회사
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Priority to KR1019950061453A priority Critical patent/KR0170524B1/en
Publication of KR970055557A publication Critical patent/KR970055557A/en
Application granted granted Critical
Publication of KR0170524B1 publication Critical patent/KR0170524B1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/02—Arrangements for detecting or preventing errors in the information received by diversity reception
    • H04L1/06—Arrangements for detecting or preventing errors in the information received by diversity reception using space diversity

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Radio Transmission System (AREA)

Abstract

본 발명은 신호 위상 감지장치에 관한 것으로 두 신호에 대한 이상의 리이드와 래그(Lead-Lag)를 정확하게 감지하도록 하는 신호위상 감지장치에 관한 것이다.The present invention relates to a signal phase detection device and a signal phase detection device for accurately detecting abnormal leads and lag (Lead-Lag) for two signals.

종래의 신호 위상 검출장치는 신호 입력단(RF1, RF2)에 입력된 신호에 대한 위상차의 절대값은 감지할 수 있으나, 두 신호에 대한 리이드 및 래그는 감지할 수 없으므로 스페이스 다이버시티(Space Diversity)수신시스템에는 적용할 수없게되는 문제점이 있다.Conventional signal phase detection device can detect the absolute value of the phase difference with respect to the signal input to the signal input terminal (RF1, RF2), but can not detect the lead and lag for the two signals, so receiving space diversity (Space Diversity) There is a problem that is not applicable to the system.

본 발명은 인가되는 두 신호에 대한 위상의 리이드와 래그를 정확하게 감지하므로 스페이스 다이버시티 수신 시스템에 적용할 수 있다. 또한 위상에러를 펄스 형태로 출력하지 않고 연속적인 값으로 출력하므로 루프 필터와 같은 적분기를 사용하지 않더라고 위상에러 값을 곧바로 확인할 수 있다.The present invention can be applied to a space diversity reception system because it accurately senses the lead and lag of a phase for two applied signals. In addition, since the phase error is output as a continuous value rather than in the form of a pulse, the phase error value can be immediately checked without using an integrator such as a loop filter.

Description

신호 위상 감지장치Signal phase detection device

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제2도는 본 발명에 따른 신호 위상 감지장치의 구성도.2 is a block diagram of a signal phase detection apparatus according to the present invention.

Claims (2)

신호 위상 감지장치에 있어서 제1입력단(P1)을 통해 인가되는 신호를 위상 지연없이 출력함과 동시에 소정각도 만큼 위상 지연시켜 출력하는 제1위상지연회로(10a)와; 제2입력단(P2)을 통해 인가되는 신호를 위상 지연없이 출력함과 동시에 소정각도 만큼 위상 지연시켜 출력하는 제2위상지연회로(10b)와; 상기 제1위상지연회로(10a)로부터 인가되는 소정각도 만큼 위상 지연된 신호와 상기 제2위상지연회로(10b)로부터 인가되는 위상 지연되지 않은 신호를 혼합하여 출력하는 제1믹서(20a)와;상기 제1위상지연회로(10a)로부터 인가되는 위상 지연되지 않은 신호와 상기 제2위상지연회로(10b)로부터 인가되는 소정각도 만큼 위상 지연된 신호를 혼합하여 출력하는 제2믹서(20b)와;상기 제1믹서(20a)로부터 인가되는 신호에서 상기 제2믹서(20b)로부터 인가되는 신호를 감산하여 감산 결과 신호를 출력하는 감산부(30)를 포함하는 것을 특징으로 하는 신호 위상 감지장치.A first phase delay circuit (10a) for outputting a signal applied through a first input terminal (P1) without a phase delay and outputting a phase delayed by a predetermined angle in a signal phase sensing device; A second phase delay circuit (10b) for outputting a signal applied through the second input terminal (P2) without phase delay and at the same time with a phase delayed output; A first mixer 20a for mixing and outputting a phase delayed signal by a predetermined angle applied from the first phase delay circuit 10a and a non-phase delayed signal applied from the second phase delay circuit 10b; A second mixer 20b for mixing and outputting a phase delayed signal applied from the first phase delay circuit 10a and a signal delayed by a predetermined angle applied from the second phase delay circuit 10b; And a subtractor (30) for subtracting the signal applied from the second mixer (20b) and outputting the subtracted result signal from the signal applied from the first mixer (20a). 제1항에 있어서 상기 제1 및 제2위상지연회로(10a)(10b)는 인가받은 신호를 90°만큼 위상 지연시켜 출력하는 것을 특징으로 하는 신호 위상 감지장치.2. The signal phase sensing device according to claim 1, wherein the first and second phase delay circuits (10a) (10b) output a phase delay of the applied signal by 90 degrees. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950061453A 1995-12-28 1995-12-28 Signal position detecting apparatus KR0170524B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950061453A KR0170524B1 (en) 1995-12-28 1995-12-28 Signal position detecting apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950061453A KR0170524B1 (en) 1995-12-28 1995-12-28 Signal position detecting apparatus

Publications (2)

Publication Number Publication Date
KR970055557A true KR970055557A (en) 1997-07-31
KR0170524B1 KR0170524B1 (en) 1999-03-30

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Application Number Title Priority Date Filing Date
KR1019950061453A KR0170524B1 (en) 1995-12-28 1995-12-28 Signal position detecting apparatus

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100424181B1 (en) * 2001-12-21 2004-03-24 주식회사 하이닉스반도체 Apparatus and method for generating output clock signal having a controlled timing

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100424181B1 (en) * 2001-12-21 2004-03-24 주식회사 하이닉스반도체 Apparatus and method for generating output clock signal having a controlled timing

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Publication number Publication date
KR0170524B1 (en) 1999-03-30

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