JPH02158210A - Pulse abnormality detection circuit - Google Patents
Pulse abnormality detection circuitInfo
- Publication number
- JPH02158210A JPH02158210A JP31247988A JP31247988A JPH02158210A JP H02158210 A JPH02158210 A JP H02158210A JP 31247988 A JP31247988 A JP 31247988A JP 31247988 A JP31247988 A JP 31247988A JP H02158210 A JPH02158210 A JP H02158210A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- period
- abnormal
- circuit
- abnormality detection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 title claims abstract description 18
- 238000001514 detection method Methods 0.000 title claims description 12
- 230000002159 abnormal effect Effects 0.000 claims abstract description 19
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は一定周期で入力するパルスの異常だけでなく、
これらパルスの間に異常パルスが混合した場合も検出し
、パルス異常信号を出力するパルス異常検出回路に関す
る。[Detailed Description of the Invention] (Field of Industrial Application) The present invention is applicable not only to abnormalities in pulses input at a constant period, but also to
The present invention relates to a pulse abnormality detection circuit that detects even when an abnormal pulse is mixed between these pulses and outputs a pulse abnormal signal.
（従来の技術）
従来、この種のパルス異常検出回路は、モノマルチ回路
？１つ使づた構成となってい念。(Prior art) Conventionally, this type of pulse abnormality detection circuit is a monomulti circuit? Please note that the configuration uses only one.
（発明が解決しようとする課題）
上述し九従来のパルス異常検出回路は、モノマルチを１
つ使つ次回路構成となっているので、入力されるべきパ
ルスが入力されない場合等のパルス異常は検出できるが
１周期Ｔ以内に異常なパルスが突出し九場合、パルスの
異常検出ができないという欠点があった。(Problems to be Solved by the Invention) The nine conventional pulse abnormality detection circuits described above
Since it has a circuit configuration that uses only one pulse, pulse abnormalities such as when a pulse that should be input is not input can be detected, but if an abnormal pulse protrudes within one period T, pulse abnormality cannot be detected. was there.
本発明の目的は上記欠点ｔ−解決するもので、周期Ｔ以
内に異常パルスが発生した場合、これを検出できるパル
ス異常検出回路全提供することにある。An object of the present invention is to solve the above-mentioned drawback T, and to provide a complete pulse abnormality detection circuit capable of detecting an abnormal pulse when it occurs within a period T.
（課題を解決するための手段）
前記目的を達成するために本発明によるパルス異常検出
回路は一足周期（Ｔ）のパルスを入力トリガとし、パル
ス＠（Ｔ−ΔＴｓ）なるパルスを出力する第１モノマル
チ回路と、前記第１モノマルチ回路から出力されるパル
スを入力トリガとし、パルス＠（Ｔ＋ΔＴ２）なるパル
スを出力する第２モノマルチ回路とからなり、前記一定
周期のパルスの間に異常パルスが混入し九とき、前記第
２モノマルチ回路が異常信号全出力するように構成しで
ある。(Means for Solving the Problems) In order to achieve the above object, the pulse abnormality detection circuit according to the present invention uses a pulse of one leg period (T) as an input trigger, and outputs a pulse @ (T - ΔTs). It consists of a mono multi circuit and a second mono multi circuit that uses the pulse output from the first mono multi circuit as an input trigger and outputs a pulse @ (T + ΔT2), and the abnormal pulse is detected between the pulses of the constant period. The second mono multi-circuit is configured to output all abnormal signals when the error signal is mixed.
（実 施 例） 以下、図面を参照して本発明をさらに詳しく説明する。(Example) Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第１図は本発明によるパルス異常検出回路の実施例を示
すブロック図であり、第２図は正常動ｆｉｌのタイムチ
ャート、ま友、第３図は異常パルス発往時のタイムチャ
ートである。FIG. 1 is a block diagram showing an embodiment of the pulse abnormality detection circuit according to the present invention, FIG. 2 is a time chart of normal operation fil, and FIG. 3 is a time chart of abnormal pulse generation.
ｌｉｄ期Ｔのパルス１１をモノマルチ回路１に入力する
と、モノマルチ回路１は周期ＴよりΔＴ１短いパルス幅
のパルス１２を出力する。このパルス１２はモノマルチ
回路２に入力１ｔ−Ｅ−ノマルチ回路２より周期Ｔより
ΔＴ２長いパルス幅のパルス１３が出力される。なお、
ΔＴ ｌ、ΔＴ２は本回路の検出能力を決めるものであ
り。When the pulse 11 in the lid period T is input to the mono multi circuit 1, the mono multi circuit 1 outputs a pulse 12 having a pulse width ΔT1 shorter than the period T. This pulse 12 is input to the monomulti circuit 2. A pulse 13 having a pulse width longer than period T by ΔT2 is outputted from the 1t-E-multiple circuit 2. In addition,
ΔTl and ΔT2 determine the detection ability of this circuit.
小さければ小さい程、検出能力は高くなる。ただし、零
よりは大きいものである。The smaller the size, the higher the detection ability. However, it is larger than zero.
いま、パルス１１が第２図のように正常な場合には、パ
ルス１３はリトリガされ続は常Ｋ”Ｈ＃状態である。If the pulse 11 is normal as shown in FIG. 2, the pulse 13 is retriggered and remains in the K''H# state.
しかし、第３図のパルス１１のように異常パルｘ２１が
発生すると、パルス１２のパルス２２は消滅してパルス
１３に１Ｌ”の状態が生じる。However, when an abnormal pulse x21 occurs like the pulse 11 in FIG. 3, the pulse 22 of the pulse 12 disappears and a 1L'' state occurs in the pulse 13.
つまりこの時、パルス１１に異常が生じ友ということが
検出でき、モノマルチ回路２の出力は異常状態を示す”
Ｌ”状態となる。In other words, at this time, an abnormality occurs in the pulse 11, and it can be detected that the pulse 11 is abnormal, and the output of the monomulti circuit 2 indicates an abnormal state.
It becomes L” state.
（発明の効果）
以上、説明したように本発Ｆ３Ａは周期Ｔなるパルスを
入力トリガとし、パルス幅Ｔ−ΔＴｌなるパルスを出力
する第１モノマルチ回路と前記パルスを入力トリガとし
パルス幅Ｔ十ΔＴ２なるパルスを出力する第２モノマル
チ回路で構成することにより、周期Ｔ以内に異常なパル
スが突出した場合、パルスの異常を検出できるという効
果がある。(Effects of the Invention) As explained above, the present invention F3A has a first monomulti circuit which takes a pulse with a period T as an input trigger and outputs a pulse with a pulse width T-ΔTl, and a first monomulti circuit which takes the pulse as an input trigger and outputs a pulse with a pulse width T By configuring the second monomulti circuit that outputs a pulse of ΔT2, there is an effect that if an abnormal pulse protrudes within the period T, an abnormality in the pulse can be detected.
第１図は本発明によるパルス異常検出回路の実施例を示
すブロック図、第２図は正常な場合のタイムチャート、
第３図は異常な場合のタイムチャートである。
ｌ・・・パルス＠Ｔ−ΔＴｌのパルス１２ｔ−出力する
モノマルチ回路
２・・・パルス幅Ｔ＋ΔＴ２のパルス１３１ｔｌ力する
モノマルチ回路
１１・・・周期Ｔのパルス
１２・・・モノマルチ回路ｌの出力パルス１３・・・モ
ノマルチ回路２の出力パルス（異常検出アラーム）
２１・・・異常パルス
２２・・・正常なパルス１１による正常なパルス１２の
ひとつのパルス
才１図
才２図
２３図FIG. 1 is a block diagram showing an embodiment of the pulse abnormality detection circuit according to the present invention, FIG. 2 is a time chart in a normal case,
FIG. 3 is a time chart in an abnormal case. l...Pulse @T-ΔTl pulse 12t-Mono multi circuit 2 outputting...Pulse 131tl with pulse width T+ΔT2 Mono multi circuit 11...Pulse 12 with period T...Mono multi circuit l Output pulse 13...Output pulse of monomulti circuit 2 (abnormality detection alarm) 21...Abnormal pulse 22...One pulse of normal pulse 12 due to normal pulse 11
Claims (1)
Ｔ−ΔＴ＿１）なるパルスを出力する第１モノマルチ回
路と、前記第１モノマルチ回路から出力されるパルスを
入力トリガとし、パルス幅（Ｔ＋ΔＴ＿２）なるパルス
を出力する第２モノマルチ回路とからなり、前記一定周
期のパルスの間に異常パルスが混入したとき、前記第２
モノマルチ回路が異常信号を出力するように構成したこ
とを特徴とするパルス異常検出回路。A pulse with a constant period (T) is used as an input trigger, and the pulse width (
It consists of a first monomulti circuit that outputs a pulse with a pulse width of T-ΔT_1), and a second monomulticircuit that uses the pulse output from the first monomulticircuit as an input trigger and outputs a pulse with a pulse width of (T+ΔT_2). , when an abnormal pulse is mixed between the pulses of the constant period, the second
A pulse abnormality detection circuit characterized in that a monomulti circuit is configured to output an abnormal signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31247988A JPH02158210A (en) | 1988-12-09 | 1988-12-09 | Pulse abnormality detection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31247988A JPH02158210A (en) | 1988-12-09 | 1988-12-09 | Pulse abnormality detection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02158210A true JPH02158210A (en) | 1990-06-18 |
Family
ID=18029706
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31247988A Pending JPH02158210A (en) | 1988-12-09 | 1988-12-09 | Pulse abnormality detection circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02158210A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02266269A (en) * | 1989-04-07 | 1990-10-31 | Toshiba Corp | Abnormality detecting circuit |
-
1988
- 1988-12-09 JP JP31247988A patent/JPH02158210A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02266269A (en) * | 1989-04-07 | 1990-10-31 | Toshiba Corp | Abnormality detecting circuit |
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