JPS6272022A - Lsi system clock supervisory method - Google Patents

Abstract

PURPOSE:To eliminate the need to provide a supervisory output terminal newly as long as a clock output terminal is already provided by composing the signal of a clock detection result and a clock output signal. CONSTITUTION:If a clock system 1 stops owing to the stop of an external clock 1 or the trouble of a frequency divider 1, that appears in the clock output as it is. Further, if the external clock 2 is cut off, the output of an AND gate 16 does not vary, so the clock output does not vary even when the clock system 1 is normal. If a frequency divider 12 becomes abnormal, a pulse stop detecting circuit 13 or 14 detects the stop, so the output of a NOR gate 15 falls to 'L', the output of the AND gate 16 is fixed at 'L', and there is not variation at the clock output terminal even when the clock signal 1 is normal. The clock output terminal is connected to a pulse stop detection part 16 provided outside an LSI and the clock stop is detected.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to system clock monitoring inside an LSI, and particularly to a method for monitoring an LSI clock having a plurality of clock systems.

2. Description of the Related Art Conventionally, this type of clock monitoring has involved providing the same number of clock stop detection circuits as the number of clock systems and new dedicated terminals for outputting the monitoring results.

FIG. 2 shows an example of the configuration of a conventional system clock monitoring method. In the figure, 21 is a frequency divider for producing internal clock thread 1 from external clock 1. 22 is a frequency divider for generating internal clock systems 2 and 3 from external clock 2; 23 is a circuit for detecting the stoppage of the clock thread 1; 24.25 is a circuit that detects the stoppage of the clock system 2.3. Reference numeral 26 denotes an OR gate which takes the logical sum of the outputs of the pulse stop detection circuits 23 to 25 and outputs it to the outside of the LSI as a clock stop signal.

Next, the operation of the above conventional example will be explained. When the external clock 1 stops, the output of the frequency divider 21 stops, so
When the clock output stops, the pulse stop detection circuit 2
3 detects a stop, so a clock stop signal is output. Furthermore, even if the frequency divider 22 fails, the pulse stop detection circuits 24 and 25 detect the stop, so a clock stop signal is output.

In this way, even with the conventional system clock monitoring method described above, it is possible to detect the stoppage of the external clock or the stoppage of the internal clock due to a failure of the frequency divider or the like inside the LSI.

Problems to be Solved by the Invention However, in the conventional LSI internal system clock monitoring method described above, a terminal is added to newly output the monitoring results, and one clock is used to monitor other clocks. Since this is a method of monitoring clocks, there was a problem in that it could not be detected if multiple clocks stopped at the same time.

The present invention solves such conventional problems, and if a clock output terminal is already provided, an excellent system clock that can improve the clock stop detection ability without the need to newly provide a monitoring output terminal is provided. It is an object of the present invention to provide a method for monitoring ivy.

Means for Solving the Problems In order to achieve the above object, the present invention includes a circuit for synthesizing a clock stop detection result and a clock output signal, and outputs the monitoring result using a clock output terminal. A monitoring target L with a clock output signal provided outside the LSI
The SI is designed to be monitored by a pulse stop detection section independent of the SI.

Operation The present invention has the following effects due to the above-described configuration. That is, since the clock stop detection result and the clock output signal are combined, if a clock output terminal is already provided, there is no need to newly provide a monitoring output terminal.

In addition, since the configuration is such that the clock output stops even if any clock system among multiple clocks stops, it is possible to monitor the clock output with a monitoring circuit installed outside the LSI to ensure more reliable operation. Can detect clock stoppage.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 1, 11 is the external clock 1 to the clock system 1.
It is a frequency divider that creates a D-free frequency, and its output is connected to other internal circuits.

It is connected to the D input terminal of the Pflossop circuit CD-F/F) 17. 12 is the external clock 2 to the black thread 2, 3
The output terminal is connected to other internal circuits and is also connected to the pulse stop detection circuit 13, 14. The pulse stop detection circuits 13 and 14 are
A circuit for detecting clock stoppage of clock system 2 and clock system 3 monitors time using an external clock 2. 15 is a NOR circuit, which is a pulse stop detection circuit 13゜1
Based on the calibration results of step 4, the output is applied to AND gate 16.
This logical sum output is supplied to one input terminal of the . 16 is an AND gate which performs an AND operation between the output terminal of the NOR circuit 15 and the external clock 2, and is connected to the C input terminal of the D-F/F 17. The output of D-F/F17 is connected to the terminal as a clock output. Reference numeral 18 denotes a pulse stop detection section provided outside the LSI, which monitors the clock output.

Next, the operation of the above embodiment will be explained. In the above embodiment, it is assumed that the external clock 2 is sufficiently faster than the internal clock thread 1. Now, the pulse stop detection circuit 13.
If 14 is not judged to be stopped, 16 Noah Gate 15
The output of is rHJ, and the output of AND gate 16 is:
External clock 2 is displayed. D-F/F17 D
Since the clock system 1 is input to the input and the external clock 2 is input to the C input terminal, the clock thread 1 synchronized with the external clock 2 is output as the clock output. Next, when the clock system 1 stops due to a stop of the external clock 1 or a failure of the frequency divider 11, this is directly reflected in the clock output. Furthermore, when the external clock 2 stops, the output of the AND gate 16 does not change, so even if the clock thread 1 is normal, the clock output does not change. If the frequency divider 12 fails, the pulse stop detection circuit 13
14 detects a stop, the output of the NOR gate 15 becomes rLJ, the output of the AND gate 16 does not change at rLJ, and even if the clock thread 1 is normal, the clock output terminal does not change.

The clock output terminal is connected to a pulse stop detection section 18 provided outside the LSI, and can detect clock stop.

In this way, according to the above embodiment, the logic circuit element 15,
Providing a synthesis section consisting of 16,1 terminals has the advantage that there is no need to newly provide a monitoring output terminal. Further, according to the above embodiment, it is possible to reliably detect any abnormality even if any external clock stops, or even if one of the internal clock threads stops due to a failure in the LSI internal circuit. .

Effects of the Invention As is clear from the above description, the present invention synthesizes the clock detection result and the clock power signal, so if a clock output terminal is already provided, a new monitoring output terminal is provided. It has the advantage that it is not necessary. Furthermore, since the clock output is stopped even if any clock system among the plurality of clocks stops, clock stoppage can be detected more reliably.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a system clock monitor according to an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional system clock monitor. 11... Frequency divider circuit, 12... Frequency divider circuit, 13...
Pulse stop detection circuit, 14...Pulse stop detection circuit, 15...Nor gate, 16...AND gate, 17...D-furinone 0 Flosoff" circuit,
18... Pulse stop detection section, 21... Frequency divider, 22... Frequency divider, 23... Pulse stop detection circuit, 24... Pulse stop detection circuit , 26...
...Pulse stop detection circuit, 26...OR gate.

Claims (1)

[Claims] An LSI comprising a plurality of clock stop detection circuits and a circuit that synthesizes the detection results and a clock output signal, and outputs the monitoring results using a clock output terminal.
How to monitor system clock.