JPH04160918A - Clock failure detecting circuit - Google Patents

Abstract

PURPOSE:To detect any duty failure and synchronous width failure by providing the clock failure detecting circuit with the function that two types of delay signals are output which are synchronous with an objective inspection clock signal and which mutually have a time difference of about half of a cycle of the objective inspection clock and that even when the condition of either one changes, the change of the condition is detected as trouble and alarm is exerted outside. CONSTITUTION:Two types of delay signals C and D are output that mutually have a time difference of about half of a cycle of an objective inspection clock signal. A state holding section 2 receives the objective inspection clock signal and delay signals C and D, and uses two sets of flip-flop circuits to hold the state of the objective inspection clock signal at a point that logic levels of delay signals C and D change from '0' to '1', and inverses the state of logic level of state signal E while outputting state signal F as it is. Abnormality detecting section 3 receives state signals E and F, and outputs, if even either one presents an abnormal state, or logic level '0', an alarm signal to terminal B.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a tarock fault detection circuit.

[Conventional technology]

Conventional clock failure detection circuits have mainly been of the type using a multivibrator as shown in FIG. This circuit first applies an operating signal to the terminal J, and then inputs a clock signal to the terminal K to start up at regular intervals and always maintains the level at the terminal at a level indicating normality. At this time, the holding time of the multivibrator is determined by the values of an external capacitor C and a resistor R (hereinafter referred to as external constants). If the period of the clock signal input to terminal K is longer than the holding time of the multivibrator determined by this external constant, the normal state cannot be maintained, the level of terminal K changes, and a fault is detected.
It is designed to be displayed.

Next, operations in the event of four typical types of failures in the clock signal will be described.

The operation diagram in FIG. 7 shows a case where the tarok signal is stuck at logic level "0" and the next signal does not come out.

An operating signal is applied to the terminal J to set it in the operating state, and when the terminal receives the first input at time p and is activated, the output of the terminal rises, and from then on, as long as the terminal K continues to receive the clock signal, the normal state will be maintained. Hold. Here, after receiving the last clock signal at time q, if no clock signal is received at terminal K even after the output time width specified by the external constant has elapsed, the output from terminal R at time r. falls, detecting a failure in the clock signal.

The operation diagram of FIG. 8 shows a case where the clock signal is stuck at logic level "1" and remains in the rising state until the next signal. In this case as well, if no clock signal is received at terminal K even after the output time width specified by the external constant has elapsed after receiving the last clock signal at time S,
At time t, the output of the terminal falls, detecting a failure in the clock signal.

The operation diagram in FIG. 9 shows the operation when a duty failure and a synchronization width failure occur in the clock signal.

Even if a duty failure occurs between time U and time V and between time W and time X during the same operation as in FIG. 6, if the cycle width is normal, time V and time Since the clock signal is received at terminal K at X, the output at terminal K does not change and cannot be detected as a fault. Furthermore, even if a cycle width failure occurs between time y and time Z and between time Z and time aa, as long as this cycle width is within the holding time specified by the external constant of the multivibrator shown in Figure 6, , the output of the terminal does not change and it is impossible to detect it as a fault.

The operation diagram in FIG. 10 shows the operation when an intermittent failure occurs in the clock signal.

When an intermittent failure occurs, the failure is detected as a periodic abnormality and the time a
The output from the terminal falls at time b, and rises again at time ac. At this time, if the time width between time ab and time ac does not satisfy the specifications of the receiving element of the fault detection signal, it is impossible to detect it as a fault.

[Problem to be solved by the invention]

The conventional clock fault detection circuit described above uses a hold time specified by an external constant of the multivibrator as a criterion for fault detection, and detects a potential change at the input terminal within this hold time. Therefore, there is a problem in that it may not be possible to detect when a duty fault or a synchronization width fault occurs. In addition, the multivibrator used in the clock failure detection circuit is an analog circuit that requires adjusting the values of the external capacitor C and resistor R, and considering that the other circuits are digital circuits, adjustment is complicated. There is also a problem.

An object of the present invention is to provide a clock failure detection circuit that uses only digital circuits that do not require adjustment as components and is capable of detecting any duty failure and period width failure.

[Means to solve the problem]

The clock failure detection circuit of the present invention receives clock signals under test, each of which is synchronized with the clock signal under test, and each of which is approximately half the period of the clock signal under test.
a delay means for outputting two types of delayed signals with a time difference of a period; two sets of state holding means for each of the two types of delayed signals as a clock signal and the clock signal to be inspected as an input signal; This configuration includes abnormality detection means for detecting a change in the state of any one of the outputs of the state holding means as an abnormality and outputting an alarm to the outside.

In the clock failure detection circuit of the present invention, the state holding means may be a flip-flop.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

A delay circuit section 1 connected to a terminal A into which a clock signal to be tested is input outputs two types of delay signals C and D having a time difference of approximately one-half period of the clock signal to be tested. The state holding unit 2 stores the clock signal under test and the delay signal C,
D, and using two sets of flip-flop circuits,
The state of the clock signal under test is maintained at the change point of the logic level of the delay signal C1D from "O°" to "°1", and the state signal E is
inverts the logic level state and outputs the state signal F as it is. The abnormality detection unit 3 receives a status signal E.

F is received, and if either one shows an abnormal state, that is, logic level "0", an alarm signal is output to terminal B.

Next, operations in the event of four typical types of failures in the clock signal under test will be described.

The operation diagram in Figure 2 shows that the clock signal under test is at logic level “
This shows a case where the signal is stuck at 0'' and the next signal does not come out.

In response to the fact that the clock signal to be tested changes from logic level "O" to 1" at time a, the delay circuit section 1 converts the delayed signal C, which has already been delayed by four-thirds of a period, to four-fifths. A delayed signal is output at time C, which is delayed by a period. The state holding unit 2 receives the delayed signals C and D at times I and C, holds the logic level states of the clock signals under test, and outputs them as state signals E and F, respectively. This operation is repeated every time the clock signal to be tested is received. At time d, the clock signal under test that should have been output reaches the logic level "
Suppose that it is stuck at 0”.

The state holding unit 2 holds this stacked state at time e using a delayed signal of the clock signal to be tested one cycle before,
The abnormality detection section 3 receives the state signal F from the logic level "1" to "0" and outputs an alarm signal to the terminal B.

The operation diagram in Figure 3 shows that the clock signal under test is at a logic level.
This shows a case where the signal is stuck at "1" and remains in the rising state until the next signal.

The operation of each circuit when the clock signal under test is normal is as follows.
This is the same as that explained in FIG. At this time, time f
Assume that the clock signal to be tested, which should originally fall, is stuck at a logic level of 1'°. The state holding unit 2 holds this stacked state at time g using the delayed signal C of the clock signal to be tested one cycle before, changes the state signal E from the logic level "1 to 0", and Upon receiving the signal, the abnormality detection section 3 outputs an alarm signal to the terminal B.

The operation diagram in FIG. 4 shows the operation when a duty failure occurs in the clock signal to be tested.

At the clock time, the logic level of the clock signal under test is “0”.
Suppose that the ratio of °′ has increased. The state holding unit 2 holds this duty fault state using the delayed signal of the clock signal to be tested one cycle before at time i, and changes the state signal F from the logic level "1" by one cycle of the clock signal. “0”
Upon receiving this, the abnormality detection section 3 outputs an alarm signal to the terminal B. Similarly, assume that at time j, the ratio of the logic level "1" of the clock signal to be tested increases. The state holding unit 2 holds this duty fault state using the delayed signal C of the clock signal under test one cycle before the time, and changes the state signal E from the logic level "1" by one cycle of the clock signal. The abnormality detection unit 3 receives this and outputs an alarm signal to the terminal B.

The operation diagram in FIG. 5 shows the operation when a synchronization width failure of the clock signal occurs.

Assume that a synchronization width abnormality occurs in one cycle of the clock signal to be inspected starting from time l due to an intermittent failure or the like. This synchronization width fault is similar to the case where the clock signal under test is stuck at the logic level "O" as described above, and the state holding unit 2 detects the delayed signal of the clock signal under test that appears to be an intermittent fault at time m. The state signal F is changed from logic level "1" to "0" by one period of the clock signal,
Upon receiving this, the abnormality detection section 3 outputs an alarm signal to terminal B. Similarly, assume that the period of the clock signal to be tested becomes longer at time n. The state holding unit 2 holds this synchronization width fault at time O using the delayed signal C of the clock signal under test that is assumed to be a synchronization width fault, and sets the state signal E to the logic level "1" for one cycle of the clock signal. The abnormality detection unit 3 receives this and outputs an alarm signal to the terminal B.

〔Effect of the invention〕

As described above, the present invention provides a delay means that outputs two types of delayed signals that are synchronized with a clock signal under test and have a time difference of approximately one half of the period of the clock signal under test; Two sets of state holding means each using these two types of delayed signals as clock signals and the clock signal to be inspected as an input signal, and an abnormality even if any one of the outputs of these two sets of state holding means changes state. By providing an abnormality detection means that detects the error and outputs an alarm to the outside, the system can be configured with only digital circuits that do not require adjustment as constituent elements, and any duty fault or synchronization width fault can be detected. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is an operation diagram when the clock signal under test is stuck at logic level "0", and FIG. 3 is a diagram of the operation when the clock signal under test is stuck at logic level "0".
Figure 4 is a diagram of the operation when the clock signal under test is stuck at 1", Figure 4 is the diagram of the operation when the clock signal under test has a due-day failure, Figure 5 is the diagram of the operation when there is a synchronization width failure of the clock signal, and Figure 6 is the conventional clock failure detection circuit. 7 is an operation diagram when the clock signal of the conventional clock failure detection circuit is stuck at logic level ``0'', and FIG. 8 is a diagram of the operation when the clock signal of the conventional clock failure detection circuit is stuck at logic level ``1''. Figure 9 is an operation diagram when the clock signal of the conventional clock failure detection circuit has a duty failure and synchronization width failure, and Figure 10 is the tally signal of the conventional tally failure detection circuit. 1 is an operation diagram when an intermittent failure occurs. 1...delay circuit section, 2...state holding section, 3...abnormality detection section, A, B. ...Terminal, C, D...Delay signal, E, F...Status signal. Agent Patent attorney Uchihara Otouri T[D 7N"J'29 U'Ti1N ? Ur-f+T't't
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Claims (1)

[Claims] 1. Two types of clock signals that receive a clock signal to be tested, each of which is synchronized with the clock signal to be tested, and have a time difference of approximately half the period of the clock signal to be tested. a delay means for outputting a delayed signal; two sets of state holding means for each of the two types of delayed signals as a clock signal and the clock signal under test as an input signal; 1. A clock failure detection circuit comprising abnormality detection means for detecting a change in state of any one as an abnormality and outputting an alarm to the outside. 2. The clock failure detection circuit according to claim 1, wherein said state holding means comprises a flip-flop.