JPS63215139A - Detecting system for fault of signal in balanced double-current interchange - Google Patents

Abstract

PURPOSE:To detect a fault even when the disconnection or the short-circuit of a single line or both lines of a balanced double-current interchange line, or the fault at a reception part are generated, by using a means which monitors a duty factor. CONSTITUTION:The titled system is provided with a duty factor monitoring part 1 being constituted of first counter 3 to monitor the signal width of the space part of a reception signal, an inverter 4 which inverts the reception signal, second counter 5 which inputs an inverted signal from the inverter 4 to monitor the signal width of the mark part of the reception signal, and an OR gate 6 which supplies the OR of the output signals outputted from two counters 3 and 5 when abnormality occurs in the reception signal, and a fault information output part 2 to output a bit of fault in formation from the duty factor monitoring part 1 to the outside, and the monitoring of the abnormality of the reception signal generated at the time of generating the disconnection of the single or both lines or the short-circuit of the balanced double- current interchange line is performed. In such a way, it is possible to detect the fault even when the disconnection or the short-circuit of the single or both lines of the balanced double-current interchange line, and the fault at the reception part are generated.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for detecting received signal failure from a balanced double-current interconnection line, and in particular, to detect failures in received signals from a balanced double-current interconnection line, particularly when one line and an object line of a balanced line are disconnected or short-circuited. This invention relates to a method for detecting faults such as duty factor abnormalities in received signals.

(Prior Art) Conventionally, failure detection of a received signal from a balanced double-current interconnection line has been performed by detecting a disconnection of the received signal when both wires of the balanced double-current interconnection line are disconnected or short-circuited. For example, a received signal detecting section configured with a monostable multi-pipe rake or the like monitors the period of the received signal, and outputs fault information indicating whether or not the manually input signal has been interrupted.

[Problem that the invention seeks to solve]

The conventional signal fault detection method described above detects the physical condition that both lines of the balanced double-current interconnection line are disconnected or short-circuited, and the signal is disconnected at the receiver, so only one line of the balanced line is disconnected. Or, if a signal is received whose period is normal but the duty factor is abnormal due to a short circuit or reception abnormality in the receiver,
The disadvantage is that failures cannot be detected.

It is an object of the present invention to eliminate such drawbacks and to detect signal disturbances in balanced double-current interconnection lines, which can detect faults even in the event of single-line disconnection, single-line disconnection, short circuit, or failure in the receiving section. The object of the present invention is to provide a detection method.

[Means for solving problems]

The signal failure detection method in a balanced double-current interconnection line according to the present invention includes: a first counter for monitoring the signal width of a space portion of a received signal; an inverter for inverting the received signal;
In order to monitor the signal width of the mark portion of the received signal, a second counter inputs the signal inverted by the inverter, and an OR gate that provides a logical sum of the output signals output from the two counters when the received signal is abnormal. and a fault information output part for outputting fault information from the duty factor monitoring part to the outside, and detects one line break, line break, or short circuit of the balance line. It is characterized by monitoring abnormalities in received signals that sometimes occur.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart of signal waveforms at various parts.

This signal failure detection method consists of a duty factor monitoring unit 1 that monitors the duty factor of a received signal and generates failure information, and a failure information unit that outputs the failure information generated in the duty factor monitoring unit 1 to the outside. It has an output section 2. The duty factor monitoring unit 1 includes an m-ary counter 3 with a cent input for monitoring the signal width of the space portion of the received signal, an inverter 4 for inverting the received signal, and an inverted received signal as input and an input signal of the received signal. An n-ary counter 5 with a reset input for monitoring the signal width of the mark part, and these two counters 3 and 5 when the received signal is abnormal.
and an OR gate 6 which calculates the logical sum of the output signals output from the .

The value m (positive integer) of the m-adic counter 3 is set so that the digits overflow when counting the number of clocks corresponding to the signal width larger than the signal width of the space part of the normal received signal of the duty factor. do. On the other hand, the value n (positive integer) of the n-ary counter 5 will overflow when the number of clocks corresponding to the signal width larger than the signal width of the mark part of the normal received signal of the duty factor is counted. Set to . Further, the failure information output unit 2 is configured with a monostable multi-bi-break or the like.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG.

The waveform of the received signal a with a normal duty factor is
As shown in the figure. The received signal a is the mark part a.

and the time T of one cycle consisting of the space part a2, the space time M in one cycle, and the mark time N in one cycle
Consists of.

Now, assume that a received signal a with a normal duty factor is input to the duty factor monitoring section 1. When the mark portion a1 is input to the m-ary counter 3, the m-ary counter 3 is reset.

On the other hand, the received signal a is inverted by the inverter 4, and when the mark part of the inverted signal is inputted to the n-ary counter 5, n
The advance counter starts counting operation in response to the failure detection clock C. Since the mark time N in one period T is normal, the n-ary counter 5 does not cause overflow, and therefore does not output a fault information output pulse to the OR gate 6.

Next, when the space portion a2 of the received signal a is input to the m-ary counter 3, the n-ary counter 5 is reset on the one hand, and the m-ary counter 3 starts counting by the fault detection clock C on the other hand. Since the space time M is normal, the m-adic counter 3 does not overflow, and therefore does not output a failure information output pulse to the OR gate 6.

Therefore, when the duty factor of the received signal is normal, the duty factor monitoring section 1 does not output fault information, so that it can be detected that the received signal is normal.

Next, as shown in FIG. 2, the operation when a received signal a' with an abnormal duty factor is input to the duty factor monitoring section 1 will be explained.

It is assumed that this received signal has a mark time changed to N'(>N) and a space time changed to M''(<M). This received signal a' is inverted by the inverter 4, and the mark of the inverted signal b' is changed to When the number is input to the n-ary counter 5, n
The advance counter starts counting operation in response to the failure detection clock C. Since N'>N, the n-ary counter 5 overflows and outputs a failure information output pulse to the OR gate 6 until it is reset. This output signal d of the n-ary counter 5 is shown in FIG.

Next, the space part a2 of the received signal a' is input to the m-ary counter 3.
, the m-adic counter starts counting by the failure detection clock C. Since the relationship M′<M exists, the m-adic counter 3 does not cause overflow, and therefore does not output the fault information output pulse to the OR gate 6. The output signal e of the m-ary counter 3 is shown in FIG.

The OR gate 6 takes the logical sum of the output signals d and e, and inputs the fault information output pulse f to the fault information output section 2. The fault information output unit 2 holds the fault information for a certain period of time after receiving the fault information output pulse f, and outputs it to the outside as a fault signal g.

On the other hand, if the received signal has an abnormal duty factor of N''<N and M'>M, the m-ary counter 3 causes a digit shift and outputs a fault information output pulse to the OR gate 6.

Therefore, if the duty factor is abnormal,
Since a failure information pulse is always output from the m-ary counter 3 or the n-ary counter 5, a failure is detected when a signal indicating that the duty factor is abnormal is received as a result of the failure information pulse being output from the OR gate 6. becomes possible.

〔Effect of the invention〕

As explained above, by using means for monitoring the duty factor, the present invention can detect faults even in the event of one line break, one line break, a short circuit, or a fault in the receiving section of a balanced double current interconnection line. There is an effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a time chart of signals of various parts. 1...Duty factor monitoring section 2...
Fault information output unit 3...M-ary counter 4...Inverter 5...N-ary counter 6...OR gate agent Patent attorney Yoshiyuki Iwasa Figure 1

Claims (1)

[Claims] (1) a first counter for monitoring the signal width of the space portion of the received signal; an inverter for inverting the received signal;
In order to monitor the signal width of the mark portion of the received signal, a second counter inputs the signal inverted by the inverter, and an OR gate that provides a logical sum of the output signals output from the two counters when the received signal is abnormal. It has a duty factor monitoring section consisting of a duty factor monitoring section, and a fault information output section for outputting fault information from this duty factor monitoring section to the outside. A signal failure detection method in a balanced double-current interconnection line, characterized by monitoring received signals for abnormalities.