JPH02260728A - Ais detecting system - Google Patents

Abstract

PURPOSE:To reduce the erroneous detection of AIS due to an inputted data error by counting the number of signals (0) from a detecting part, and outputting the AIS when the number of signals (0) is less than that of signals (0) possible to occur at an allowable error rate. CONSTITUTION:The detecting part 10 outputs a pulse only when inputted data DATA shows (0). A time to judge the AIS is set on a timer, and the number of pulses outputted from the detecting part within that time is counted by a counter 21. When the number of pulses exceeds that of signals (0) at the allowable error rate i.e., when input DATA is not the AIS, the pulse is outputted to an RS flip-flop 22, and a signal representing that the DATA is not the AIS is outputted from the flip-flop 23 of a D-latch. In such a way, it is possible to reduce the erroneous detection of the AIS, and furthermore, to reduce the number of elements in a counter part.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is directed to AIS (^larm In) of a transmission communication device.
dication Signal: alarm display signal) detection method.

[Conventional technology]

Conventionally, AIS detection in transmission communication equipment uses both consecutive 2-bit data, or
DATA is recognized as 1 only when either one is 1. Then, /US detection is performed by counting the obtained 1 data.

An example of a conventional AIS detection method that performs ATS detection in this manner is shown in FIG. This AIS detection method is
AIs are detected from input data DATA.

This conventional AIS detection method consists of a detection section 3o and an output section 4.
It consists of 0.

The detection unit 30 includes flip-flops 31 and 32, an OR gate 33, and an AND gate 34, and receives data DATA and a clock signal CLK.

Such a detection unit 3o detects the data DA when both or either of the consecutive 2-bit data is “1”.
TA as “1”! ! Understand.

This recognized data of °'1'' is sent to the output section 4o.

The output section 40 includes a counter 41 and a flip-flop 42.
．． 43 and a timer 44, to which the clock signal CLK and data from the detection section 30 are input.

Such an output section 30 counts 1'' data from the detection section 30 and detects the ATS.Then, the ATS is outputted from the terminal Q of the flip-flop 43.

[Problem to be solved by the invention]

In the conventional AIS detection method described above, in order to prevent false detection, if both or either of the consecutive 2-bit data is "1 pass", it is recognized that the data DATA is "1".For this reason, When continuous DATA of "01" is input to the conventional AIS detection method, an operation that erroneously detects AIS is performed.

Furthermore, since the number of counts of obtained "l" data is large, the number of elements in the counter section is also large.

This has the drawback of hindering cost reduction and space saving on the unit.

SUMMARY OF THE INVENTION An object of the present invention is to provide an AIS detection method that can eliminate such drawbacks, reduce erroneous detection of AIs, and also reduce the number of elements in the counter section.

[Means to solve the problem]

The present invention provides an AIS detection method that outputs an ATS indicating an abnormality in a transmission communication device based on input data, which includes: a detection section that detects a "0" signal of input data; and a "0" signal from the detection section. '0' signal is counted and this '0' signal is counted.
It is characterized by having an output section that outputs AIS when the error rate is less than the number of zero signals that can occur at an error rate that the number of signals allows.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention. This AIS detection method includes a detection section 10 and an output section 20.

Further, the detection section 10 is composed of an inverter 11 and an AND gate 12.

The output unit 20 includes a counter 21 and
Flip-flop 22.23 and timer (TIMER)
It consists of 24.

In the AIS detection method having such a configuration, the detection unit 10
The inverter 11 inverts the input data DATA. The inverted data is output to the AND gate 12.

AND gate 12 performs a logical product operation between the signal from inverter 11 and clock signal CLK. The calculation result is output to the output section 20.

The timer 24 sets the time for determining AIS based on the clock signal input to the terminal C.

A signal related to this setting is output to the terminal R of the counter 21, the terminal R of the flip-flop 22, and the terminal C of the flip-flop 23.

The counter 21 receives and receives pulses from the AND gate via the terminal C, and counts these pulses for the time set by the timer 24. Then, based on the counted number of pulses, the pulses are output to the terminal S of the flip-flop 22.

Flip-flop 22 outputs a signal from terminal Q based on the signal from counter 21 and the signal from timer 24. This signal is input to the terminal of the flip-flop 23.

Based on the signal from the flip-flop 22 and the signal from the timer 24, the flip-flop 23 outputs from the terminal Q a signal indicating AIS or non-AIS.

Next, the operation of this embodiment will be explained.

A clock signal CLK is inputted to the toggle 2 of the detection section 10 and the terminal C of the timer 24 of the output section 20.

Based on this clock signal CLK, the timer 24
The time for determining IS is set.

Then, a signal related to this setting is output from the terminal OUT. This signal is input to the terminal R of the counter 21, the terminal R of the flip-flop 22, and the terminal C of the flip-flop 23.

In such a state, continuous data DATA of, for example, 01'' is input to the inverter 11 of the detection unit 10.The inverter 11 inverts this data DATA.The inverted data is input to the AND gate 12. is input.

The AND gate 12 performs a logical AND operation between the inverted data from the inverter 11 and the clock signal CLK,
Output the calculation result.

As a result, when the input data DATA is II On, the detection section 10 sends out a pulse to the output section 20.

The pulse from the detection section 10 is sent to the counter 21 of the output section 20.
is input to terminal C of. Counter 21 counts this pulse for the time set by timer 24. Then, the counter 21 outputs a pulse from the terminal CO when the number of pulses exceeds the number of pulses corresponding to the number of "0" signals that can occur at the allowable error rate, that is, when the input data DATA is not AIS. do.

The pulse from the counter 21 is the flip-flop 22
is input to terminal S of. Based on this signal, the flip-flop 22 outputs a signal from the terminal Q to the terminal of the flip-flop 23.

In response to the signal from the flip-flop 22, the flip-flop 23 outputs a signal from the terminal Q indicating that the data DATA is not AIS.

Next, data DATA of “1” is input to the detection unit 10. The inverter 11 inverts this data DATA and outputs it to the AND gate 12. Therefore, no pulse is sent from the AND gate 12 to the output section 20.

Since no pulse is input to the counter 21 of the output section 20, the counter does not output a pulse from the terminal CO. Based on this state, the flip-flop 23 outputs AIS in response to a signal from the flip-flop 22.

In this way, according to this embodiment, the detection unit 10 outputs a pulse only when the input data DATA is 0''.The timer 24 is set with a time for determining AIS,
A counter 21 counts the pulses output from the detection section 10 within that time. Then, when the number of "0" signals that can occur at the error rate allowed by the number of pulses is reached, that is, when the input DATA is not AIS, a pulse is output to the RS flip-flop 22, and the pulse is output from the flip-flop 23 of the D latch. A signal indicating that the data DATA is not AIS is output.

〔Effect of the invention〕

As explained above, the present invention changes the conventional ATS detection using the "l" signal to detection using the "'0" signal, and sets the detection time and number of counters to appropriate values to prevent input data errors. The resulting erroneous detection of ATS can be reduced, and the resulting reduction in the number of counters reduces the number of elements for counting, leading to cost reduction and space saving on the unit.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 2 is a circuit diagram showing an example of a conventional AIS detection method. 10... Detection unit If... Inverter 20... 21... 22, 23, 24...

Claims (1)

[Claims] (1) An AIS detection method that outputs an AIS indicating an abnormality in a transmission communication device based on input data, comprising: a detection section that detects a "0" signal of the input data; and a "0" signal from the detection section. Count the signal and this “0”
An AIS detection method comprising: an output section that outputs an AIS when the number of signals is less than the number of "0" signals that can occur at an allowable error rate.