JPH03256421A - Slip detection circuit - Google Patents

Abstract

PURPOSE:To prevent the erroneous detection of clock slip by counting the cycles of first and second clocks by using a third clock with high frequency, and comparing those two counting results with each other. CONSTITUTION:The third clock is a clock to count the cycles of the first and second clocks, respectively, and is provided with the frequency higher than that of the first and second clocks. The cycle of the first clock can be counted by a first counter means 111 and that of the second clock by a second counter means 121 by performing a counting operation synchronized with the third clock. A comparison means 131 compares the two counting results with each other, and a comparison result is outputted as the detection result of the clock slip. In such a manner, it is possible to detect the clock slip in spite of the phase stats of the first and second clocks, and to prevent the clock slip detected erroneously.

Description

[Detailed Description of the Invention] [Summary] In a communication device such as a time division multiplexer, a clock slip occurring between a synchronization clock used for data transmission and an internal clock used within the communication device is detected. Regarding the slip detection circuit configured as above, the slip detection circuit detects a clock slip occurring between a first clock and a second clock, with the aim of preventing erroneous detection of a clock slip. A third clock having a high clock rate is input, and a first counting means performs a counting operation synchronized with this third clock to count the period of the first clock. a second counting means that performs a counting operation to count the period of the second clock;
The counting result of the counting means and the counting result of the second counting means are inputted, and the counting means is provided with a comparing means for comparing the two counting results.

[Industrial application field]

The present invention relates to a slip detection circuit that detects a clock slip occurring between a synchronization clock used for data transmission and an internal clock used within the communication device in a communication device such as a time division multiplexer. It is something.

[Conventional technology]

Modern data transmission systems handle a large amount of various types of data, and in order to achieve a highly reliable transmission system, clocks for synchronizing the transmitted data and internal devices used in the communication equipment that make up the transmission system are required. It is necessary to detect clock slips with the clock to ensure clock synchronization.

A circuit that detects such a lock slip is a slip detection circuit.

A conventional slip detection circuit performs slip detection using the respective edges (rising or falling) of two manually generated clocks, namely, a synchronization clock and an internal clock. For example, a synchronization clock is input to the clock terminal of a 1-bit counter, and an internal clock is manually input to the reset terminal. Therefore, if the internal clock does not rise between the rises of the synchronization clock, this
The focus counter will overflow and an alarm will be output from the carry-out terminal. Further, by using a 1-bit counter in which the input clock is switched in addition to the 1-bit counter described above, it becomes possible to mutually monitor clock slips.

[Problem to be solved by the invention]

By the way, in the above-mentioned conventional method, since only the edges of the synchronization clock and the internal clock are used, there is a problem that a clock slip is erroneously detected when jitter or the like occurs. In general, each of the synchronization clock and the internal clock has a permissible frequency range, and even if jitter occurs, normal operation is possible as long as it is within this permissible frequency range. Since there are cases where the other clock rises or falls twice between the falling edges, erroneous detection of a clock slip may occur depending on the phase relationship between the two clocks.

The present invention was created in view of these points, and an object of the present invention is to provide a slip detection circuit that can prevent erroneous detection of clock slips.

[Means to solve the problem]

FIG. 1 is a principle block diagram of the slip detection circuit of the present invention.

In the figure, a first counting means 111 in a slip detection circuit that detects a clock slip occurring between a first clock and a second clock receives a third clock having a higher frequency than the first and second clocks; A counting operation is performed in synchronization with this third clock to count the period of the first clock.

The second counting means 121 receives the third clock, performs a counting operation in synchronization with the third clock, and counts the period of the second clock.

The comparison means 131 receives the counting results of the first counting means 111 and the counting results of the second counting means 121, and compares the two counting results.

Therefore, as a whole, the clock slip is detected by comparing the periods of the first and second clocks counted by the third clock having a higher frequency.

[For production]

The third clock is for counting the cycles of the first clock and the second clock, and has a higher frequency than the first clock and the second clock.

By performing a counting operation in synchronization with the third clock, the first counting means 111 counts the period of the first clock, and the second counting means 121 counts the period of the second clock. The comparison means 131 compares the two counting results, and this comparison result is output as the clock slip detection result.

For example, when the difference between the cycles of the first clock and the second clock is outside the allowable range, a message indicating that a clock slip has been detected is output.

In the present invention, each period of the first and second clocks is counted using a third clock with a high frequency, and the two counting results are compared, and the phase states of the first and second clocks are Clock slips can be detected regardless.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of a slip detection circuit in one embodiment of the present invention.

In FIG. 2, 211 and 221 are counting circuits, 21
3 and 223 are the rising detection parts, 214°219.22
4 and 229 are flip-flops (FF), 215 and 225 are Nant gates, 217 and 227 are counters, and 231 is a comparator, respectively.

The counting circuit 211 is for counting the period of the synchronization clock, and includes a rise detection section 213 consisting of a flip-flop 214 and a Nant gate 215, a counter 217 that performs a counting operation in synchronization with the counting clock, and a counter 217. A flip-flop 219 that holds the output of .

The flip-flop 214 holds the synchronization clock input to the input terminal in synchronization with the measurement clock input to the clock terminal, and the inverted output terminal d is connected to one input terminal of the NAND game) 215. has been done.

Here, it is assumed that the counting clock has a much higher frequency than the synchronization clock. Nantes Gate 2
A synchronizing clock is manually input to the other input terminal of the counter 15, and the output terminal is connected to the reset terminal R of the counter 217.

The counter 217 performs a counting operation in synchronization with the measurement clock input to the clock terminal, and the n-bit output terminal O that outputs the counting result is connected to the flip-flop 2.
It is connected to 19 input terminals. The flip-flop 219 captures and holds the counting result of the counter 217 input to the input terminal in synchronization with the rising edge of the synchronization clock, and the n-bit output terminal Q is connected to the comparator 2.
It is connected to one input terminal P of 31.

The counting circuit 221 is for counting the period of the internal clock, and includes a rising edge detection section 223 consisting of a flip-flop 224 and a Nant gate 225, and a counter 227 that performs a counting operation in synchronization with the counting clock. Flip-flop 2 that holds the output of counter 227
It is equipped with 29.

The flip-flop 224 holds an internal clock manually input to the input terminal in synchronization with the measurement clock input to the clock terminal, and the inverted output terminal d is connected to one input terminal of the Nant gate 225. has been done.

The other input terminal of the Nant gate 225 has an internal lock input thereto, and its output terminal is connected to the reset terminal R of the counter 227.

The counter 227 performs a counting operation in synchronization with the measurement clock input to the clock terminal, and the n-bit output terminal O that outputs the counting result is connected to the flip-flop 2.
It is connected to 29 input terminals. The flip-flop 229 takes in and holds the counting result of the counter 227 inputted to the input terminal in synchronization with the rising edge of the internal clock, and the n-bit output terminal Q is connected to the comparator 2.
It is connected to the other input terminal Q of 31.

The comparator 231 compares the n-bit counting result related to the synchronization clock input to each of the two input terminals P and Q with the n-bit counting result related to the internal clock, and if these counting results are not equal, Outputs an alarm (logic °°1”) to notify the clock slip.

In order to ensure normal operation of the communication system, it is necessary to equalize each cycle of the synchronization clock and the internal clock, but strictly speaking, each cycle has a tolerance range that can guarantee operation. Therefore, the comparator 231 also needs to take this tolerance into consideration, and is configured to output an alarm when a discrepancy in the count results that exceeds the tolerance range occurs. In order to output such an alarm, for example, a human-powered
The comparison may be made using only the high-order bits of the pinto count results excluding the low-order pintos.

FIG. 3 shows the operation timing of the counting circuits 211 and 221 shown in FIG. 2. Hereinafter, details of the counting operation of the counting circuits 211 and 221 will be explained with reference to FIGS. 2 and 3.

Since the counters 217 and 227 are for counting the cycles of the synchronization clock and the internal clock, it is assumed that they do not overflow within one cycle. For example, if the frequency of the counting clock is about 10,000 times that of the synchronization clock and the internal clock, it is necessary to configure the counter with 14 bits or more.

The flip-flop 214 in the rising edge detection unit 213 takes in the input synchronizing clock in synchronization with the rising edge of the counting clock, and converts the synchronizing clock (inverted output) whose phase is shifted by one cycle of the counting clock into a Nant gate. 215 (Figure 3 (a), (b),
(C)), the synchronization clock itself is input to the other input terminal of the NAND gate 215, and the logic "'0" corresponding to the above-mentioned phase shift is output from the NAND gate 215 at the rise of the synchronization clock. A signal is output (FIG. 3(d)).

The counter 217 performs a reset operation according to the output of the Nant gate 215, and the count value is reset when the output rises. After reset, it operates in synchronization with the counting clock, and until the next reset, counting operation for one period of the maximum synchronization clock is performed (
Figure 3(e)).

The flip-flop 219 takes in and holds the count result of the counter 217 in synchronization with the rising edge of the synchronization clock immediately before resetting every cycle of the synchronization clock (FIG. 3(f)), and inputs it to the comparator 231.

Similarly, the cycle of the internal clock is counted in the counting circuit 221 ((8) to (j) in FIG. 3). O), the comparator 231 is manually operated.

In this way, the counting circuit 211 counts the period of the synchronization clock in synchronization with the counting clock, and the counting circuit 221 counts the period of the internal clock in synchronization with the counting clock.

The comparator 231 compares each of these count values, and outputs an alarm notifying a clock slip depending on the comparison result (specifically, in the case of a mismatch).

Therefore, clock slips can be detected regardless of the phase states of the synchronization clock and the internal clock, and erroneous detection can be prevented and detection accuracy can be increased.

In the embodiment of the present invention described above, by detecting the rise of two contrasting clocks, the counting operation is performed according to one period of these clocks.
The counting operation may be performed by detecting the falling edge, or the counting operation may be performed according to a plurality of cycles.

〔Effect of the invention〕

As described above, according to the present invention, each period of the first and second clocks is counted using the third clock having a high frequency and the two counting results are compared. By detecting a clock slip regardless of the phase state of the clock, false detection can be prevented, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of a slip detection circuit according to the present invention, FIG. 2 is a configuration diagram of a slip detection circuit according to an embodiment of the present invention, and FIG. 3 is an operational diagram of the embodiment. In the figure, 111 is a first counting means, 121 is a second counting means, 131 is a comparison means, 211.221 is a counting circuit, 213.223 is a rising edge detection section, 214.219, 224.229 are flip-flops (
FF), 215.225 is a Nant gate, 217.227 is a counter, and 239 is a comparator. Fukatsu θ month ψ 斥 りふ □, 7ri figure 1

Claims (1)

[Claims] (1) In a slip detection circuit that detects a clock slip occurring between a first clock and a second clock, a third clock having a higher frequency than the first and second clocks is input, and the third clock A first counting means (111) performs a synchronized counting operation to count the period of the first clock, and a first counting means (111) receives the third clock and performs a counting operation synchronized with the third clock,
a second counting means (121) for counting the period of the clock;
The counting result of the first counting means (111) and the counting result of the second counting means (121) are input, and the comparing means (131) is configured to compare the two counting results. Features a slip detection circuit.