KR100366800B1 - Apparatus for detecting error of external clock in transmission system - Google Patents

Abstract

The present invention, in the external clock error detection device of the transmission system, a reference signal generator for generating a reference clock signal using the low-frequency internal clock signal, and initializes the counter using the reference clock signal generated by the reference signal generator A counter control unit for outputting a control signal for detecting a counter value, a counter for counting a time when an external clock signal is high using a reference clock signal generated by the reference signal generator and a control signal of the counter control unit, The present invention provides an external clock error detecting apparatus for a transmission system including a final determination unit determining whether the external clock is normal by checking a counter value output from the counter.

As described above, the present invention enables to check a high frequency signal as a low frequency signal so that an error of a high frequency external clock can be checked without a separate high frequency signal.

Description

Apparatus for detecting error of external clock in transmission system}

The present invention relates to an external clock error detection device of a transmission system. In particular, when a signal is processed using an external clock as a reference for synchronizing equipment in a transmission system, a high frequency signal is used by using an internal clock signal of a low frequency. The present invention relates to an external clock error detection device of a transmission system that enables inspection and is suitable for checking an error of a high frequency external clock even without a separate high frequency signal.

In general, a transmission system processes signals using an external clock as a reference to synchronize equipment.

1 is a block diagram showing a board for processing data using an external clock in such a general transmission system.

Therefore, when the data signal is input to the block for processing the data signal using the data signal and the external clock signal and the external clock, the block outputs the processed data signal, and the inputted external clock signal uses the internal clock to determine whether the external clock is normal. It is also input to the block for determining the output signal that tells the processor whether the external clock is normal in this block.

In order to determine whether an arbitrary clock is normal, the clock signal in the board of the same or higher frequency as the incoming external clock is used.

2 is a block diagram of an external clock determination unit of a conventional transmission system.

As shown in the figure, a counter 11 which receives an external clock and an internal clock and counts during the time that the external clock is high; An external clock determination unit including a counter value checking unit 12 for receiving an output of the counter 11 to check a counter value and outputting a signal for checking whether the counter value is normal and informing a result to an external processor ( 10).

The conventional apparatus configured as described above checks the clock using a signal having a higher frequency than the incoming clock.

That is, using the internal clock of the high frequency available in the counter 11, the incoming external clock counts a signal that is high, and sends the result to the counter value confirming unit 12. Then, the counter value checking unit 12 determines whether or not the counter value results in a normal value and informs the outside.

For example, if the incoming external clock is a signal with a frequency of 10KHz, and the available internal clock has a frequency of 100KHz, the external clock has a period of 10 times that of the internal clock, so that the external clock is high. The time is five times the internal clock. That is, if the time when the external clock is high is counted using the internal clock, the value becomes 5.

3 is a clock waveform diagram of FIG.

Thus, if the value of counting the external clock using the internal clock is "5" as in "①" of FIG. 3, the external clock is recognized as normal, and the count value is not "5" as in the "②". If the value is determined, the external clock is determined to be not normal and the result is reported to the external processor.

However, if the internally available clock has a lower frequency than the externally incoming clock, it becomes impossible to use the conventional circuit as shown in FIG. In other words, the conventional apparatus has a limitation in that it operates only when the frequency of the inner clock is higher than the frequency of the incoming external clock.

Accordingly, the present invention has been proposed to solve the conventional problems as described above, and an object of the present invention is an internal clock of low frequency when processing a signal using an external clock as a reference to synchronize equipments in a transmission system. It is an object of the present invention to provide an external clock error detection device of a transmission system that can check a high frequency signal using a signal and check an error of a high frequency external clock without a separate high frequency signal. In the present invention, in the external clock error detection apparatus of the transmission system, a reference signal generator for generating a reference clock signal using the internal clock signal of the low frequency, and a counter using the reference clock signal generated by the reference signal generator A counter control unit for initializing and outputting a control signal for detecting a counter value; The counter which counts the time when the external clock signal is high using the reference clock signal generated by the generation unit and the control signal of the counter control unit and the final value of the external clock is determined by checking the counter value output from the counter. It provides an external clock error detection device of a transmission system composed of a determination unit.

1 is a block diagram showing a board for processing data using an external clock in a general transmission system,

2 is a block diagram of an external clock determination unit of a conventional transmission system;

3 is a clock waveform diagram of FIG. 2;

4 is a block diagram of an external clock error detection apparatus of a transmission system according to the present invention;

5 is a detailed circuit diagram of a reference signal generator of FIG. 4;

6 is a detailed circuit diagram of the counter control unit in FIG. 4;

7 is a detailed circuit diagram of the counter in FIG.

FIG. 8 is a detailed circuit diagram of the final determination unit in FIG. 4;

FIG. 9 is a waveform diagram when the clock is in a steady state in FIG. 4;

FIG. 10 is a waveform diagram when the clock is in error in FIG.

Explanation of symbols on the main parts of the drawings

20: reference signal generation unit 30: counter control unit

50: counter 60: final judgment

Hereinafter, an embodiment according to the technical concept of the external clock error detection apparatus of the present invention as described above is as follows.

4 is a block diagram of an external clock error detection apparatus of a transmission system according to the present invention.

The present invention includes a reference signal generator 20 for generating a reference clock signal having a clock cycle of a sufficient high frequency by using a low frequency internal clock signal; A counter controller 30 for initializing a counter by using the reference clock signal generated by the reference signal generator 20 and outputting a control signal for detecting a counter value; A counter (50) for receiving a reference clock signal generated by the reference signal generator (20) and a control signal of the counter controller (30) to count a time when the reference clock signal is high; The final determination unit 60 is configured to determine whether the external clock is normal by checking the counter value output from the counter.

As shown in FIG. 5, the reference signal generator 20 receives a high signal input and a low frequency internal clock signal to generate a first T flip-flop that generates a clock signal that is twice as small as a period of the internal clock signal. 21; A second T flip-flop (22) for receiving the output of the first T flip-flop at a clock stage and generating a clock signal that is twice as small as a period of the input clock signal; A third T flip-flop that receives the output of the second T flip-flop into a clock stage and outputs a clock signal having a cycle twice smaller than the input clock signal period, a signal having the cycle smaller twice, and a signal inverted in phase; 23).

6, the counter controller 30 includes: a delay unit 31 for receiving and delaying a signal having an appropriate high frequency clock period output from the reference signal generator 20; The control signal output unit 41 receives an output signal of the reference signal generator 20 and an output signal of the delay unit 31 and outputs a signal for controlling the counter 50.

In this case, the delay unit 31 receives a signal having an appropriate high frequency clock period output from the reference signal generator 20 and delays the signal by the period of the inputted internal clock signal to output the first D flip-flop 32. )and; A second D flip-flop (33) for receiving the output of the first D flip-flop (32) and delaying the input by the period of the input internal clock; A third D flip-flop 34 which receives a phase inverted signal with respect to a signal having a clock frequency of an appropriate high frequency output from the reference signal generator 20 and delays it by a period of the inputted internal clock signal 34 and; The fourth D flip-flop 35 is configured to receive the output of the third D flip-flop 34 and delay the output by the period of the internal clock signal.

The control signal output unit 41 includes: a plurality of logic logic elements 42 to 45 which respectively receive the output of the reference signal generator 20 and the output of the delay unit 31 and perform logical sum operations; A plurality of D flip-flops 46 to 49 are respectively outputted by delaying the signals output from the negative logic elements 42 to 45 by a period of an internal clock signal.

As shown in FIG. 7, the counter 50 receives the output of the reference signal output unit 20 and the external clock, and outputs the signal from the control signal output unit 41 in the counter control unit 30. A plurality of hexadecimal counters 52 and 56 for counting a case in which the clock is abnormal based on the reference numerals; A plurality of logical sum elements (53) (57) for performing an OR operation on each of the outputs of the plurality of hexadecimal counters (52) (56); D flip-flops 54 and 58 for delaying the output of the plurality of logical sum elements 53 and 57, respectively.

As shown in FIG. 8, the final judging unit 60 includes: a logical sum element 61 for receiving an output of a plurality of D flip-flops 54, 58 in the counter 50 and performing an OR operation; It is composed of a D flip-flop (62) for receiving the output of the logic sum element 61 to the clock stage to delay and output a signal that determines whether the external clock is normal.

The operation of the external clock error detection apparatus of the transmission system according to the present invention configured as described above will be described in detail with reference to the accompanying drawings.

First, the reference signal generator 20 generates clock signals REF_1 and REF_2 that are 16 times smaller than a period of the external clock signal using the low frequency internal clock LOCALCLK signal. That is, the first T flip-flop 21 receives a low frequency internal clock signal LOCALCLK to the clock input terminal, and simultaneously receives a signal having a high voltage to the T input terminal to receive a clock signal that is twice as small as the period of the internal clock LOCALCLK. And output to Q output terminal.

The second T flip-flop 22 receives a clock signal that is twice as small as a period of LOCALCLK output from the Q output terminal of the first T flip-flop 21 to the clock terminal, and inputs a signal having a high voltage to the T input terminal. The signal is output to the Q output terminal having a period two times smaller than the input clock signal period, that is, four times smaller than the period of the LOCALCLK.

In addition, the third T flip-flop 23 receives a clock signal having a period four times smaller than the period of the LOCALCLK output from the Q output terminal of the second T flip-flop 22 to the clock terminal, and receives a signal having a high voltage. A clock signal having a period 2 times smaller than the input clock signal cycle, that is, 8 times smaller than the cycle of LOCALCLK, is output to the Q output stage to output the REF_1 signal, and the output signal of the Q output stage and the clock are input to the input stage. The signal inverted signal phase is output to the QN output terminal to output the REF_2 signal.

Then, the counter controller 30 receives the reference signal generated by the reference signal generator 20 to initialize the counter and outputs a control signal for checking the counter value.

That is, the delay unit 31 receives and delays a signal having an appropriate high frequency clock period output from the reference signal generator 20, and the control signal output unit 41 outputs the output signal of the reference signal generator 20. And the output signal of the delay unit 31 and outputs a signal for controlling the counter 50.

Thus, the first D flip-flop 32 in the delay unit 31 receives LOCALCLK as the clock input terminal, receives the REF_1 signal output from the third T flip-flop 23 into the D input terminal, and converts the REF_1 signal to the LOCALCLK signal period. It delays by and outputs the REF_1_01 signal. The second D flip-flop 33 receives the LOCALCLK signal through the clock input terminal, receives the REF_1_01 signal output from the first D flip-flop 32 into the D input terminal, and delays the signal by the period of the LOCALCLK signal to output the REF_1_02 signal. do.

In addition, the third D flip-flop 34 in the delay unit 31 receives LOCALCLK as the clock input terminal, receives the REF_2 signal output from the third T flip-flop 23 into the D input terminal, and transmits the REF_2 signal to the LOCALCLK signal. It delays by and outputs the REF_2_01 signal. In addition, the fourth D flip-flop 35 receives the LOCALCLK signal to the clock input terminal, receives the REF_2_01 signal output from the third D flip-flop 34 to the D input terminal, delays the LOCALCLK signal by a period, and outputs the REF_2_02 signal. do.

The first negative logic element 42 in the control signal output unit 41 performs a negative logic operation on the REF_1_01 signal inverted with the REF_1 signal and the REF_1_02 signal inverted. The second negative logic element 43 performs an NOR operation on the REF_1 signal and the REF_1_02 signal inverted with the REF_1 signal. The third negative logic element 44 performs a negative logic sum operation on the REF_2_01 signal inverted with the REF_2 signal and the REF_2_02 signal inverted. In addition, the fourth negative logic element 45 performs an NOR operation on the REF_2 signal, the REF_2_01 signal, and the inverted REF_2_02 signal.

In addition, the first D flip-flop 46 in the control signal output unit 41 receives the LOCALCLK as the clock input terminal, receives the output of the first negative logic element 42 as the D input terminal, and delays the input signal by the period of the LOCALCLK. To output the CHK_1 signal through the Q terminal. This CHK_1 signal becomes a clock signal for checking whether the external clock is normal while the REF_1 signal is high.

In addition, the second D flip-flop 47 receives the LOCALCLK as the clock input terminal, receives the output of the second negative logic element 43 as the D input terminal, and delays the input signal by the period of the LOCALCLK to receive the CLR_1 signal through the Q terminal. Will print. This CLR_1 signal becomes a clear signal for resetting the counter 50 after confirming normality by the CHK_1 signal.

Furthermore, the third D flip-flop 48 receives the LOCALCLK as the clock input terminal, receives the output of the third negative logic element 44 as the D input terminal, delays the input signal by the period of the LOCALCLK, and sends the CHK_2 signal through the Q terminal. Will print. This CHK_2 signal becomes a clock signal for checking whether the external clock is normal while the REF_2 signal is high.

In addition, the fourth D flip-flop 49 receives the LOCALCLK as the clock input terminal, receives the output of the fourth negative logic element 45 as the D input terminal, and delays the input signal by the period of the LOCALCLK, thereby transmitting the CLR_2 signal through the Q terminal. Will print. This CLR_2 signal becomes a clear signal for resetting the counter 50 after confirming normality by the CHK_2 signal.

When the control signal is output in this way, the counter 50 receives the reference signal generated by the reference signal generator 20 and the control signal of the counter controller 30 to count the time when the reference signal is high.

That is, the first hexadecimal counter 52 receives the CLR_1 signal to the CD input terminal, the REF_1 signal to the CI and SP input terminal, and receives the external clock EXTCLK to the clock input terminal while the CI and SP are high. The LSB C0 and the MSB Q0 to Q3 are counted. In the second hexadecimal counter 56, the CLR_2 signal is input to the CD input terminal, the REF_2 signal is input to the CI and SP input terminal, and the external clock EXTCLK is input to the clock input terminal, and the LSB while CI and SP are high. Counts C0 and MSB, Q0 to Q3.

In addition, the first logical sum element 53 performs an OR operation on the C0, Q0, Q1, Q2, and inverted Q3 signals at the output terminal of the first hexadecimal counter 52, and the second logical sum element 57 performs the first hexadecimal counter. At the output terminal of 56, the C0, Q0, Q1, Q2, and inverted Q3 signals are ORed.

Then, the first D flip-flop 54 in the counter 50 receives CHK_1 as the clock terminal, receives the output of the first logical sum element 53 as the D input terminal, and delays the signal delayed by the period of CHK_1 through the Q terminal. Will output The CKF_1 signal indicates whether a clock error is detected by CHK_1. When the signal is high, the CKF_1 signal indicates that an external clock has an error. In addition, the second D flip-flop 58 in the counter 50 receives CHK_2 as a clock terminal, receives the output of the second AND gate 57 as the D input terminal, and delays the signal delayed by a period of CHK_2 through the Q terminal. Will output The CKF_2 signal indicates whether or not a clock error is detected by CHK_2. If the signal is high, the CKF_2 signal indicates that an external clock has an error.

Meanwhile, the final judging unit 60 determines whether the external clock is normal by checking the counter value output from the counter 50.

That is, the logical sum element 61 in the final determination unit 60 receives the CKF_1 and CKF_2 signals and performs the logical sum operation to output the CKF signal. This CKF signal is a final signal indicating whether an external clock has an error. If the signal is high, the CKF signal is in the FAIL state.

The D flip-flop 62 in the final judging unit 60 receives the CLR_F signal to the CD input terminal, the CKF signal of the logical sum element 61 to the clock input terminal, and the signal having the high voltage to the D input terminal receives the CKF_F signal. Will print Here, the CLR_F signal is a clear signal for resetting the CKF_F signal, and the CKF_F signal is a flag signal of the CKF signal.

9 is a waveform diagram when the clock is in the normal state in FIG. 4, and FIG. 10 is a waveform diagram when the clock is in the error state in FIG.

Therefore, it is possible to determine whether the clock is error by the CKF and CKF_F signals that are finally output.

As described above, the present invention enables checking of a high frequency signal as a low frequency signal, thereby checking an error of a high frequency external clock without a separate high frequency signal.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the external clock error detection apparatus of the transmission system according to the present invention enables a high frequency signal check as a low frequency signal, so that a separate high frequency signal is unnecessary for the external clock check. .

Claims (7)

In the external clock error detection device of the transmission system, A first T flip-flop that generates a clock signal that is twice as small as the period of the internal clock signal using a low frequency internal clock signal, and a clock signal that is twice as short as the period of the output signal of the first T flip-flop A second T flip-flop, a clock signal that is twice as short as the period of the output signal of the second T flip-flop, and a third T flip-flop that outputs a clock signal whose phase is inverted. A reference signal generator for generating a reference clock signal; A counter controller which initializes a counter by using the reference clock signal generated by the reference signal generator and outputs a control signal for detecting a counter value; A counter for counting a time when the external clock signal is high by using the reference clock signal generated by the reference signal generator and a control signal of the counter controller; Apparatus for detecting the external clock error of the transmission system, characterized in that the final determination unit for determining whether the external clock is normal by checking the counter value output from the counter. delete The method of claim 1, wherein the counter control unit, A delay unit which receives and delays a signal having an appropriate period output from the reference signal generator; And a control signal output unit configured to receive an output signal of the reference signal generator and an output signal of the delay unit to output a signal for controlling the counter. The method of claim 3, wherein the delay unit, A first D flip-flop that receives a signal having an appropriate period output from the reference signal generator and delays the signal by an input period of the internal clock; A second D flip-flop for receiving the output of the first D flip-flop and delaying the output by the period of an internal clock; A third D flip-flop that receives a phase inverted signal with respect to a signal having an appropriate period output from the reference signal generator and delays the signal by a period of an input internal clock; And a fourth D flip-flop configured to receive the output of the third D flip-flop and delay the output by the period of the internal clock to output the fourth D flip-flop. The method of claim 3, wherein the control signal output unit, A plurality of negative logic elements configured to receive the output of the reference signal generator and the output of the delay unit and perform logical sum operations; And a plurality of D flip-flops for delaying a signal output from each negative logic element by a period of an internal clock, and outputting the respective D flip-flops. The method of claim 1, wherein the counter, A plurality of hexadecimal counters for receiving an output of the reference signal output unit and an external clock and counting an abnormal clock based on a signal output from a control signal output unit in the counter control unit; A plurality of logical sum elements configured to OR the outputs of the plurality of hexadecimal counters, respectively; And a D flip-flop for delaying outputs of the plurality of logical sum elements, respectively. The method of claim 1, wherein the final determination unit, A logic sum element configured to receive an output of the plurality of D flip-flops in the counter and perform an OR operation; And a D flip-flop configured to output a signal for determining whether an external clock is normal by delaying the output of the logical sum element through a clock stage.