JPH0495426A - Crc error check circuit - Google Patents

Abstract

PURPOSE:To prevent a state of no CRC error from being outputted by latching a CRC operation result so as to be a prescribed period or less in a state corresponding to no CRC error when a data of all 1 or all 0 is inputted. CONSTITUTION:A frame reference timing detection means 1 detects a reference timing of a frame of a reception data. A CRC residue arithmetic means 3 calculates a CRC residue of the reception data. A CRC error check timing generating means 2 generates a timing to be latched based on a reference timing. A CRC arithmetic result latch means 4 latches the result of arithmetic operation of the means 3 in a latched timing. A consecutive 0s/1s detection means 5 detects it that a data equal to 0 is consecutive for a prescribed range in the reception data or a data equal to 1 is consecutive for a prescribed range in the reception data. A mask means 6 masks an output of the means 4 when the means 6 detects it that a data equal to 0 is consecutive for a prescribed range or a data equal to 1 is consecutive for a prescribed range.

Description

[Detailed Description of the Invention] [Summary] Regarding a CRC error detection circuit that detects bit errors in transmitted data, it is necessary to avoid outputting a CRC error-free state when received data is all 1s or all 0s. a frame reference timing detection means for detecting a reference timing of a frame of received data; a CRC remainder calculation means for calculating a CRC remainder of the received data; and a CRC remainder calculation means for generating the latch timing based on the reference timing. CR
C error detection timing generation means; CRC calculation result latch means for latching the calculation result of the CRC remainder calculation means at the latching timing; and in the received data, data equal to 0 is continuous within a predetermined range;
Alternatively, a 0 series/1 series detection means detects that the data equal to 1 is continuous in a predetermined range, and the data equal to O is continuous in a predetermined range, or the data equal to 1 is detected in a predetermined range. and masking means for masking the output of the CRC operation result latch means when it is detected that the CRC operation results are consecutive.

[Industrial application field]

The present invention relates to a CRC error detection circuit that detects bit errors in data transmitted between units within a device.

CRC error detection has been conventionally performed to detect bit errors in data transmitted between digital transmission devices via a transmission path, but it is also used within digital transmission devices to remotely control devices, For automatic switching in the event of a failure, control signals and A
Error detection is also required when transmitting data such as LM signals.

[Prior art and problems to be solved by the invention] Part 6
The figure shows a configuration for CRC error detection used in a receiving section of a conventional optical transmission device.

In FIG. 6, 39 is an optical transmission line, 40 is a photoelectric conversion unit,
41 is a synchronization detection section, 42 is a pattern generation section, and 4
3 is a CRC error detection section.

The optical signal transmitted via the optical transmission line 39 is transmitted to the photoelectric conversion unit 4
At 0, the signal is converted into an electrical signal, and at that time, timing (clock) extraction, data identification, and input disconnection detection are performed. The synchronization detection section 41 includes a photoelectric conversion section 40
The frame synchronization is detected by inputting the data and clock obtained in , and the timing of the beginning of the frame is provided to the pattern generating section 42 . The CRC error detection unit 43
The data and clock obtained by the photoelectric conversion section 40 are input to perform calculations for CRC error detection, and the pattern generation section 42 generates timing for latching the output of the CRC error detection section 43.

The latched output of the CRC error detection unit 43 indicates whether or not the data of the received frame contains a CRC error, that is, the presence or absence of a CRC error.
Only when there is no error, the data of the received frame is taken into the transmission device.

By the way, as mentioned above, even within a digital transmission device, there are configurations for transmitting data such as control signals and ALM signals between units (packages) for remote control of the device and automatic switching in the event of a failure, for example. The result will be as shown in FIG. That is, the data input/output section of each package is provided with a communication LSI, respectively.
The transmission path side of each communication LSI is connected to a high potential level via a resistor. Therefore, when no data is being transmitted between the communication LSIs, all 1s are input to the communication LSIs.

As shown in FIG. 8, the communication LSI in FIG.
It is equipped with a configuration for C error detection.

That is, the communication LSI shown in FIG. 7 includes a synchronization detection section 41, a pattern generation section 42, and
It also has a configuration corresponding to the CRC error detection section 43.

However, as shown in FIG. 8, the communication LSI used for data transmission between packages does not have a configuration for detecting an input disconnection, so when an input disconnection occurs, the CR
All 1 data is input to the C error detection section. By the way, when all 1 or all O data is input to the CRC error detection section, the output of the CRC error detection section repeats the same pattern at a constant cycle, and
- A state corresponding to no CRC error occurs at a certain period.

The CRC error detection timing from the pattern generator is periodically output in synchronization with a free-running clock due to input interruption. As mentioned above, the output of the CRC error detection section is latched at the timing of CRC error detection from the pattern generation section, but the output of the CRC error detection section is
The timing at which the state corresponding to no C error occurs and the timing at which the CRC error is detected from the pattern generation section match at the least common multiple of the respective periods, so even if the input data is all I's or all O's, , the state corresponding to no CRC error is latched at the above matching timing, and the all 1 or all 0 data at that time is taken in as normal data. That is, there is a problem in that data in an error state is input as normal data.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a CRC error detection circuit that does not output a CRC error-free state when received data is all 1s or all O's. It is something.

[Means to solve the problem]

FIG. 1 is a basic configuration diagram of the present invention.

In FIG. 1, 1 is a frame reference timing detection means, 2 is a CRC error detection timing generation means, and 3 is a CRC
Remainder calculation means, 4 CRC operation result latch means, 5 O
A series/single series detection means, and 6 a masking means.

Frame reference timing detection means 1 detects the reference timing of a frame of received data.

The CRC remainder calculating means 3 calculates the CRC remainder of the received data.

The CRC error detection timing generation means 2 generates the latch timing based on the reference timing.

The CRC calculation result latch means 4 latches the calculation result of the CRC remainder calculation means 3 at the latching timing.

The 0 series/1 series detection means 5 detects 0 in the received data.
Continuous data equal to within a given range, or
It is detected that data equal to 1 is continuous within a predetermined range.

The masking means 6 masks the output of the CRC calculation result latch means 4 when it is detected that the data equal to 0 continues in a predetermined range or that the data equal to 1 continues in a predetermined range. do.

[For production]

The predetermined range in the 0/1 series detection means 5 is:
As mentioned above, when all 1 or all O data is input, the output of the CRC operation result latch means 4 becomes CR.
If the setting is made so that the period is below a certain period that corresponds to no error, when all 1 or all 0 data is input in the above range, the masking means 6 will check the CRC.
The output of the arithmetic result latch means 4 is masked, and if the received data is all 1's or all 0's, it will no longer output a CRC error-free state.

〔Example〕

FIG. 2 shows the configuration of the O-unit/1-unit detection means 5 in the embodiment of the present invention. FIG. 3 shows one of the operations when data 1 is continuously input to the configuration shown in FIG.
FIG. 4 shows an example of the operation when data 1 is continuously input to the configuration of FIG. 2.

In FIG. 2, 11 and 14 are inverters, 12 is an AND circuit, 15 and 22 are OR circuits, 13, and 16 to 21 are flip-flop circuits.

Reception data is input to the data input terminal of the flip-flop circuit 13, and reception clock is input to the edge trigger input terminal.

As shown in FIG. 3, when level 1 data is applied to the flip-flop circuit 13, the -Q of the flip-flop circuit 13 is applied at the rising edge of the next clock.
-The output falls, and this output is applied to the negative logic set input terminal S of the flip-flop circuit 16, setting the flip-flop circuit B16. The Q output of the flip-flop circuit 16 is applied to the D input terminal of the flip-flop circuit 17;
The output is applied to the D input terminal of the flip-flop circuit 18.

Similarly, as shown in FIG. 4, when data at level O is applied to the flip-flop circuit 13, the flip-flop circuit 13 at the rising edge of the next clock.
The Q output of No. 3 falls, and this Q output is applied to the negative logic cent input terminal S of the flip-flop circuit 19 to set the flip-flop circuit 19. The Q output of the flip-flop circuit 19 is applied to the D input terminal of the flip-flop circuit 20;
The Q output of is applied to the D input terminal of the flip-flop circuit 21.

Although not shown, a pattern generation circuit is provided which is composed of a counter and a decoding circuit that decodes the output of the counter.As mentioned above, when all 1 or all O data is input (described later) ) A clock C with a constant period T is applied to the edge trigger input terminals of the flip-flop circuits 16 to 21, which is set so that the CRC calculation result latch output is equal to or less than a certain period at which the CRC operation result corresponds to no CRC error. , as shown in FIG. 3, the Q of the flip-flop circuit 16 is delayed by the period T of the clock C at the rising timing of the clock
The output state appears in the Q output of the flip-flop circuit 17 and then the Q output of the flip-flop circuit 18 in order. Similarly, as shown in FIG. 4, the state of the Q output of the flip-flop circuit 19 is delayed by the period T of the clock C at the rising timing of the clock C, and the state of the Q output of the flip-flop circuit 20 is changed to the state of the Q output of the flip-flop circuit 20. They appear in sequence at the Q output of the pull-up circuit 21.

The Q output of the flip-flop circuit 18 and the Q output of the flip-flop circuit 21 are applied to an OR circuit 22, and are ORed.
The output of the circuit 22 is a signal MASK which indicates the detection of consecutive O's or consecutive 1's in the received data and masks the output of a state in which there is no CRC error, which will be described later.

The above received data is input to one input of the AND circuit 12 and to the inverter 11, and the output of the inverter 11 is input to the other input of the AND circuit 12 to generate a reset pulse as shown in FIG. and is applied to flip-flop circuits 16-18. Further, the above received data is input to one input of the OR circuit 15 and to the inverter 1.
4, and the output of the inverter 14 is input to the OR circuit 15.
is input to the other input of the flip-flop circuits 19 to 21 by generating a reset pulse as shown in FIG.
to be applied.

1 continuous or O as shown in FIGS. 3 and 4.
When data equal to 1 or data equal to 0 are continuously input for a period of time from T11 to 2T depending on the timing of the start of the series, the Q output of the flip-flop circuit 18 or 21 becomes 1, respectively. As a result, the output MASK of the OR circuit 22 becomes 1. As an input to the OR circuit 220, the Q outputs of the flip-flop circuits 17 and 20 are used instead of the Q outputs of the flip-flop circuits 18 and 21.
If the output is taken, the output MASK of the OR circuit 22 is determined when data equal to 1 or data equal to 0 are continuously input for a period of time from 1 to T, depending on the timing of the start of consecutive 1s or consecutive 0s. can also be set to 1.

FIG. 5 shows a configuration for CRC error detection in an embodiment of the present invention.

In FIG. 5, 30 is a CRC calculation circuit, 31 is an AND
circuit, 32 is a selector, 33 is a flip-flop circuit,
And 34 is an OR circuit.

The CRC calculation circuit 30 sequentially inputs received data and a reception clock, performs a CRC calculation, and outputs a CRC remainder. All bits of the output of the CRC calculation circuit 30 are AN
is input to the D circuit 31, and the AND circuit 31 inputs the CRC
It becomes 0 when the CRC remainder calculated by the calculation circuit 30 is O. The output of the AND circuit 31 becomes one input of the selector 32, and the output of the selector 32 is applied as the D input of the flip-flop circuit 33. The above reception clock is applied to the edge trigger input terminal of the flip-flop circuit 33. The Q output of the flip-flop circuit 33 is applied as the other input of the selector 32 and one input of the OR circuit 34. The MASK signal obtained by the configuration shown in FIG. 2 described above is applied to the other input of the OR circuit 34.

The timing at which the output (remainder) of the CRC calculation circuit 30 is supposed to be O when the CRC error calculation for one frame of data without errors is completed is as described above with reference to the timing of the beginning of the frame detected by the frame synchronization circuit. The signal is supplied as a CRC error detection timing from a pattern generation circuit (not shown), and is applied as a control signal to the selector 32. The selector 32 selects the Q output of the flip-flop circuit 33 at timings other than the above-mentioned CRC error detection timing, and selects the output of the AND circuit 31 at the above-mentioned CRC error detection timing.

In this way, data indicating whether or not the output of the CRC calculation circuit 30 is 0 (that is, whether or not there is a CRC error in the data of the frame) is latched in the flip-flop circuit 33 at the CRC error detection timing. When there is no CRC error in the data, the Q output of the flip-flop circuit 33 is 0.
is output as a CRC error via the OR circuit 34. However, if the input data is all 1 or all 0
, the output of the CRC calculation circuit 30 is C
When the timing of the state corresponding to no RC error matches the CRC error detection timing from the pattern generation circuit described above, all 1s or all 0s of the input data have already been detected in the configuration shown in FIG. 2, and the OR Since the MASK signal input to the circuit 34 is 1, even if the Q output of the flip-flop circuit 33 becomes O, the output of the OR circuit 34 indicates a CRC error state, and abnormal data is detected. It will no longer be imported as normal data.

[Effects of the Invention] According to the CRC error detection circuit of the present invention, when the received data is all 1's or all 0's, a state of no CRC error is not output.

[Brief explanation of the drawing]

FIG. 1 is a basic configuration diagram of the present invention, FIG. 2 is a diagram showing the configuration of the 0/1 consecutive detection means 5 in an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of the data 1 in the configuration of FIG. 2. FIG. 4 is a diagram showing an example of the operation when data 1 is continuously input to the configuration of FIG. 2, and FIG. , a diagram showing a configuration for CRC error detection in an embodiment of the present invention, FIG.
FIG. 7 is a diagram showing an outline of the configuration for data transmission within the digital transmission device, and FIG. 8 is a diagram showing the configuration for C error detection, and FIG. FIG. 3 is a diagram showing a configuration for error detection. [Explanation of symbols] 1-Frame reference timing detection means, 2-CRC error detection timing generation means, 3-CRC remainder calculation means, 4
- CRC calculation result latch means, 0 series/1 series detection means, 6- mask means, 11.14- inverter, 12-A
ND circuit, 15.22-OR circuit, 13.16-21-
Flip-flop circuit, 30--CRC calculation circuit, 31-A N D circuit, 32--Selector, 33-
Flip-flop circuit, 34-OR circuit, 39. -Optical transmission line, 40-.-Photoelectric conversion section, 41-.Synchronization detection section, 4
2--Pattern generation section, 43-CRC error detection section.

Claims (1)

[Scope of Claims] Frame reference timing detection means (1) for detecting a reference timing of a frame of received data; CRC remainder calculation means (3) for calculating a CRC remainder of received data; CRC error detection timing generation means (2) that generates latch timing
CRC calculation result latch means (4) for latching the calculation result of the CRC remainder calculation means (3) at the latching timing; and in the received data, data equal to 0 is continuous within a predetermined range; Alternatively, a 0 series/1 series detection means (5
), and the CRC operation result latch means (4) when detecting that the data equal to 0 is continuous in a predetermined range or that the data equal to 1 is continuous in a predetermined range.
A CRC error detection circuit comprising: masking means (6) for masking the output of the CRC error detection circuit.