GB2243747A

GB2243747A - Digital signal error detecting arrangements

Info

Publication number: GB2243747A
Application number: GB9009185A
Authority: GB
Inventors: Damer Evelyn O'neil Waddington
Original assignee: Marconi Instruments Ltd
Current assignee: Marconi Instruments Ltd
Priority date: 1990-04-24
Filing date: 1990-04-24
Publication date: 1991-11-06
Anticipated expiration: 2010-04-24
Also published as: GB2243747B; GB9009185D0

Abstract

A digital signal error detecting arrangement comprises generator means (1, 3, 5, 7, 9, 11) responsive to a section of a received test signal sequence of digits thereafter to generate itself successive further digits in the test signal; and measurement means (19, 27) for comparing the generated digits with received said further digits to thereby indicate the error ratio therebetween. The operation of the measurement means (19, 27) is inhibited until the intregrity of the generated digits is established. The integrity of the generated digits is established by comparing them with the received further digits. <IMAGE>

Description

Digital Signal Error Detecting Arrangements This invention relates to digital signal error detecting arrangements.

More particularly the invention relates to such arrangements of the kind comprising: generator means responsive to a section of a received test signal sequence of digits thereafter to generate itself successive further digits in the test signal; and measurement means for comparing the generated digits with received said further digits and thereby indicate the error ratio therebetween.

In operation of such arrangements a correct indication of error ratio cannot be made until after a period of reception of the test signal without errors, i.e. until so-called synchronisation is achieved.

It is an object of the present invention to provide a digital signal error detecting arrangement wherein an indication of error ratio is effected as rapidly as possible after synchronisation is achieved.

According to the present invention a digital signal error detecting arrangement comprises: generator means responsive to a section of a received test signal sequence of digits thereafter to generate itself successive further digits of the test signal sequence; measurement means for comparing the generated digits with received said further digits and thereby indicate the error ratio therebetween; and means for inhibiting operation of said measurement means until the integrity of the generated digits has been established.

Said inhibiting means suitably establishes integrity of said generated digits by comparing them with said received further said digits.

In one particular embodiment of the invention said generator means comprises: shift register means having a length equal to said section of the received test signal; and control means for feeding to the input of the shift register a sequence of digits of the test signal of a first length at least as great as the length of the shift register and then feeding a signal derived from said shift register to the input of the shift register so as thereafter to cause generation of said further digits of the test sequence; and said inhibiting means comprises means for resetting said control means to the condition in which the test signal is fed to the input of the shift register if a generated digit differs from the contemporary received further digit until the received further digits and the generated digits have been the same for a sequence of digits of a second length as least as great as the length of said shift register, the inhibiting means then allowing operation of said measurement means.

Said first and second lengths are suitably equal to a first power of two, e.g. the first power of two greater than the length of the shift register.

In an arrangement according to the invention the measurement means suitably comprises: first counter means which counts the digits in the test signal, and second counter means which counts the number of times a generated digit differs from the contemporary received further digit, the arrangement producing an output indicating whether or not the first counter means counts Y before the second counter means counts X, where X is less than Y, thereby to indicate whether or not the error ratio is less than X errors in Y received digits.

One error detecting arrangement in accordance with the invention will now be described, by way of example, with reference to the accompanying drawing which is a block schematic diagram of the arrangement.

The arrangement indicates when the error ratio in a received test signal is below a predetermined value i.e. when not more than X of Y received test signal digits are in error.

The test signal fed to the arrangement comprises a pseudo-random sequence of binary digits of the kind that can be generated by a recirculating shift register arranged so that, on being clocked, the first stage assumes a state determined by a combination of the states of the last stage and at least one other stage.

Referring now to the drawing, the error detecting arrangement comprises a shift register 1 having Z stages whose input is supplied by way of a switching circuit comprising two AND gates 3 and 5, an OR gate 7 and an inverter 9 so that the input to the register 1 comprises either the test signal or the output of an exclusive-OR gate 11, according to the state of a first bistable reset circuit 13. The inputs of the gate 11 are derived from the shift register 1 so that when the register 1 has been appropriately initialised and the input of the shift register 1 is connected to the output of the gate 11, a sequence of digits the same as that in the test signal appears at the output of the gate 11. In the drawing a single gate 11 is shown having its inputs connected to the output of the shift register 1 and a point along the length of the register.

However it will be appreciated that other recirculating shift register feedback generator arrangements may be used.

The test signal and the output of the gate 11 are also fed to respective inputs of a two-input exclusive-OR gate 15 whose output is fed to one input of a two-input AND gate 17 whose output is applied to the input of an error counter 19 having a full count X, and to one input of a two-input AND gate 21. The output of the AND gate 21 is applied to one input of a three-input OR gate 23 whose output operates a monostable 25 whose output is applied to the reset input of the reset circuit 13. Reset pulses for the whole error detecting arrangement are applied to a second input of the OR gate 23 and the error counter 19 applies a pulse to the third input of the OR gate 23 when the counter 19 overflows.

The arrangement further includes a main counter 27 having a full count Y to whose input are fed clock pulses at the digit rate of the test signal, which pulses also control operation of the shift register 1. The counter 27 has a first tap 29 at which pulses appear at a count Z' at least as great as the length of, i.e. as the number of stages in, the shift register 1. Where the number of stages in the register 1 is not a power of two the count Z at tap 29 is suitably equal to the first power of two greater than the number of stages Z in the register 1. The pulses at tap 29 are fed to the set input of a second bistable reset circuit 31 whose output is fed to the set input of the first reset circuit 13, to the second input of AND gate 17 and one input of a three-input OR gate 33. The output of the OR gate 33 operates a second monostable 35 whose output is applied to a reset input of the error counter 19.

The main counter 27 has a second tap 37 at which pulses appear at a count 2Z', twice that at which pulses appear at the tap 29, the pulses at tap 37 being applied to the set input of a third bistable reset circuit 39 whose output is fed via an inverter 41 to the second input of AND gate 21. The counter 27 also supplies a pulse to a second input of the OR gate 33 when the counter 27 overflows.

The output of the monostable 25, in addition to being used to reset circuit 13, is used to reset the main counter 27 and the reset circuits 31 and 37 and is also applied to the third input of the OR gate 33.

The operation of the arrangement will now be described.

When an overall reset pulse is applied to the OR gate 23 the resulting pulse produced by monostable 25 sets the counts of counters 19 and 27 to zero, sets the reset circuit 13 and 31 into states such that the test signal is applied via the switching circuit 3, 7, 5, 9 to the input of register 1 and the output of gate 11 is disconnected from the input of register 1 and such that the AND gate 17 is disabled, and sets the reset circuit 39 to a state such that the AND gate 21 is enabled via the inverter 41.

The digits of the test signal are then counted by the main counter 27 and fed into the shift register 1 until the register is full, as indicated by the appearance of a pulse at the tap 29 of the main counter 27. In response to this pulse the reset circuits 31 and 13 operate to cause the switching arrangement 3, 7, 5, 9 to connect the output of the gate 11 to the input of the register 1 in place of the test signal, to enable AND gate 17 and to reset the error counter 19 to zero via the OR gate 33 and monostable 35.

The signal generated at the output of gate 11 is compared with the received test signal at the gate 15 so that a pulse is produced at the output of gate 15 if the compared generated signal and test signal digits differ. When the AND gates 17 and 21 are both enabled the occurrence of any such pulse operates the monostable 25 via AND gates 17 and 21 and OR gate 23, thereby resetting the whole arrangement and causing the series of operations described above to restart.

During filling of the register 1 the AND gate 17 is disabled so that occurrence of a pulse at the output of gate 15 does not cause resetting of the arrangement.

If no errors occurred in the test signal as the register 1 was being filled so that the test signal is correctly generated at the output of gate 11 and a further Z' digits of the test signal are then correctly received, no pulse occurs at the output of the gate 15 during receipt of the further Z' digits to cause reset via AND gate 17 (now enabled) and AND gate 21 and the count of pulses in the test signal by the main counter 27 continues after a pulse has appeared at tap 29 until a pulse appears at tap 37. This pulse causes reset circuit 39 to operate so as to disable gate 21 via inverter 41 and thereafter prevent overall reset on occurrence of an error in the received test signal. The occurrence of this pulse indicates the integrity of the digits generated at the output of the gate 11 and that a correct measurement of the error ratio in the received test signal can now be made.The output of the reset circuit 39 can be used to operate a display (not shown) to indicate this, as illustrated by the legend 'sone achieved' in the drawing.

The occurrence of an error in the received test signal during initial filling of the register 1 and/or during subsequent checking of the integrity of the digits of the signal at the output of gate 11 by comparison of such digits with the further Z' digits of the test signal at gate 15 causes gate 15 to produce an output during such checking. The resulting resetting of the arrangement via AND gates 17 and 21 thus inhibits error ratio measurement until the integrity of the digits of the generated signal has been indicated by operation of reset circuit 39.

Measurement of error ratio is effected as follows.

Each error in the test signal occurring subsequent to operation of the reset circuit 39 produces a pulse at the output of gate 15 which is counted by the error counter 19 whilst the main counter 27 continues to count the digits in the received test signal.

If Y digits are received before X errors are counted by the error counter 19, i.e. the number of errors in the test signal is within the prescribed limit, the counter 27 overflows to reset the error counter 19 to zero via OR gate 33 and monostable 35, the 'sync achieved' signal at the output of reset circuit 39 being therefore maintained. The counter 27 may also be reset at this time to check the error ratio repeatedly. If the error counter 19 overflows before the main counter 27 overflows, i.e. the error ratio exceeds the prescribed limit, the monostable 25 is caused to generate an overall reset pulse via OR gate 23, thereby removing the 'sync achieved' signal at the output of gate 39 and restarting the whole series of operations.

It will be appreciated that in the operation of the arrangement error ratio measurement will start the first time after switch-on that a sequence of error free test signal digits 2Z' long is received. Thus the arrangement is very suitable for measuring error ratio of high error ratio signals.

It will be understood whilst the arrangement in accordance with the invention described above, by way of example, is for use with a test signal comprising a particular kind of pseudo random sequence of binary digits which can be generated by a recirculating shift register with an exclusive OR gate feedback path, this is not necessarily the case. The test signal could instead, for example, comprise a cyclically repetitive sequence of digits, in which case generation of the test signal in the error detecting arrangment can be performed by a shift register of length equal to an integral multiple of the repetitive sequence whose output is fed back directly to its input.

Claims

1. A digital signal error detecting arrangement comprising: generator means responsive to a section of a received test signal sequence thereafter to generate itself successive further digits of the test signal sequence; measurement means for comparing the generated digits with received said further digits and thereby indicate the error ratio therebetween; and means for inhibiting operation of said measurement means until the integrity of the generated digits has been established.

2. An arrangement according to Claim 1 wherein said inhibiting means establishes integrity of said generated digits by comparing them with said further received test signal digits.

3. An arrangement according to Claim 2 wherein said inhibiting means and said measurement means use a common comparator means for comparing said generated digits with said further received digits.

4. An arrangement according to Claim 2 or Claim 3 wherein said generator means comprises: shift register means having a length equal to said section of the received test signal; and control means for feeding to the input of the shift register a sequence of digits of the test signal of a first length at least as great as the length of the shift register and then feeding a signal derived from said shift register to the input of the shift register so as thereafter to cause generation of said further digits of the test sequence; and said inhibiting means comprises means for resetting said control means to the condition in which the test signal is fed to the input of the shift register if a generated digit differs from the contemporary received further digit until the received further digits and the generated digits have been the same for a sequence of digits of a second length at least as great as the length of said shift register, the inhibiting means then allowing operation of said measurement means.

5. An arrangement according to Claim 4 wherein said first and second lengths are equal.

6. An arrangement according to Claim 4 or Claim 5 wherein said first and second lengths each comprise a number of digits equal to a power of two.

7. An arrangement according to Claim 6 wherein said first and second lengths each comprise a number of digits equal to the first power of two greater than the length of the shift register.

8. An arrangement according to any one of the preceding claims wherein said measurement means comprises: first counter means which counts the digits in the test signal, and second counter means which counts the number of times a generated digit differs from the contemporary received further digit, the arrangement producing an output indicating whether or not the first counter means counts Y before the second counter means counts X, where X is less than Y, thereby to indicate whether or not the error ratio is less than X errors in Y received digits.

9. An arrangement according to Claim 8 wherein when the first counter means exceeds a count of Y the second counter means is reset and when the second counter means reaches a count of X said first and second counter means are both reset and said inhibiting means inhibits operation of said measurement means until the integrity of the generated digits has again been established.

10. An arrangement according to Claim 8 or Claim 9 when dependent on any one of Claim 4 to 7 wherein said first counter means also counts the digits in the test signal during reception of said sequences of digits of a first length and a second length but is reset if a generated digit differs from a contemporary received further digit until the received further digits and the generated digits have been the same for said sequence of digits of a second length.

11. An arrangement according to Claim 10 wherein said first counter means performs the counting of the digits of said sequences of a first length and a second length required for operation of said control means and said inhibiting means.

12. A digital signal error detecting circuit substantially as hereinbefore described with reference to the accompanying drawing.