JPH04180318A - Method and circuit for synchronization protection - Google Patents

Abstract

PURPOSE:To always detect a synchronous error by identifying whether an input signal is a synchronous code word or not, and holding cumulatively or deleting the number of times of the reception of a normal synchronous code word and the number of times of the detection of an abnormal synchronous signal in conformity to a predetermined multiplying factor. CONSTITUTION:A transmitted signal is inputted to a code identifying part 21 by the ratio of one bit to every 193 bits. In accordance with whether said signal is a synchronous bit or not, the signal of a high level when the synchronous bit or the signal of a low level when of asynchronous bit is outputted from a synchronous code word identifying circuit 21a. In the case that the signal outputted from the circuit 21a is outputted as a high level signal and a low level signal at random, right shift is every one bit, and on the contrary, left shift is every two bits. Then, time when asynchronous bit is detected and all the signals outputted from a protecting part 23 are turned into the low level is earlier than the time when the synchronous bits are detected continuously, and asynchronism can easily be detected.

Description

[Detailed Description of the Invention] [Summary] Regarding a synchronization protection method and a synchronization protection circuit used in a digital conveyance device, etc., an object of the present invention is to detect a synchronization error even in a signal input in which synchronization loss occurs alternately with synchronization establishment. The purpose of this method is to identify whether an input signal is a synchronization code or not, and cumulatively store or delete the number of times a normal synchronization code is received and the number of times an abnormal synchronization signal is detected according to a predetermined multiplier. The configuration provides redundancy to protect the judgment of the match from being immediately linked to the output, and also determines whether synchronization has been established or lost the synchronization based on the ratio of the number of times held, and outputs the result as a signal. A method and apparatus.

[Industrial application field]

The present invention relates to a synchronization protection method and a synchronization protection circuit used in digital conveyance devices and the like.

[Prior Art] As shown in FIG. 3, a synchronization protection circuit in a conventional digital conveyance device includes an identification section 1, a protection section 2, and an output section 3.
It is divided into

The identification unit 1 forms a synchronization code identification circuit 4 which checks the input signal and outputs it at a high level if it is a synchronization bit sent every 193 bits, and outputs it at a low level if it is not a synchronization bit. are doing.

The protection unit 2 continues from the output of the identification unit 1 by m (in the figure, m=
2) Forms a determination circuit 5 that determines a synchronization code when a high-level code is detected, and determines a synchronization error when a high-level code is detected n consecutive times (n=4 in the figure). are doing.

The output section 3 forms an output circuit 6 that outputs a high-level signal when synchronization is established based on the determination result of the protection section 2, and outputs a low-level signal when synchronization is lost.

The determination circuit 5 includes a one-way shift register 5a (such as shift register 5N74179 manufactured by Texas Instruments) and high-level output terminals (Ql, Q2.Q3.Q,
The forward protection circuit 5b is formed by a NANDu path that inputs the output signals output from two terminals from the beginning of the terminal ('), inverts their logical product, and outputs the result. Rearward protection circuit 5 formed by a NAND circuit that inputs output signals output from four terminals from the beginning of times, ), inverts the logical product of these, and outputs the result.
It is equipped with c.

The output circuit 6 includes two NAND circuits 6a.

6b, the output signal of the forward protection circuit 5b is inputted to one input terminal of the NAND circuit 6a, and the output signal of the rear protection circuit 5c is inputted to one input terminal of the NAND circuit 6b.

The other NAND circuit 6b, 6a is connected to the other input terminal of 6b.
is formed so as to input the output signal of the NAND circuit 6.
The output signal of a is output as a confirmation signal indicating whether synchronization has been established or synchronization has been lost.

The synchronization protection by this device is implemented when a digital signal (shown in FIG. 4(a)) is input to the synchronization code identification circuit 4.
A high level signal of 1 bit every 193 bits is used as a synchronization bit, and a high level signal is output from the synchronization code identification circuit 4 (the output signal sequence is shown in FIG. 4(b)). If there is an accidental code match, the forward protection circuit 1i:85 is used to prevent the code from being determined to be a synchronous code.
When a synchronization signal is detected twice in a row, it is assumed that synchronization has been established, and when a synchronization error is detected four times in a row in the rear protection circuit 5c, a signal is sent to the output section 6. Served from.

[Problem to be solved by the invention]

In the conventional synchronization protection circuit described above, the number of consecutive detections of synchronization and overload, m, is smaller than the number of consecutive synchronization error detections, n (m x n).
Therefore, even though the synchronization was actually lost, 1 out of n times
If a code matching the synchronization code is received at any time,
There is a problem in that detection of out-of-synchronization may be delayed or may not be detected for a long time.

The present invention has been made in view of the above-mentioned problems, and the technical problem set to solve the problem is to provide a synchronization system that detects synchronization errors even in signal inputs where synchronization failures occur alternately with synchronization establishments. An object of the present invention is to provide a protection method and a synchronization protection circuit.

[Means to solve the problem]

As a specific means for solving the above problems, the present invention, as shown in FIG. The number of times an abnormal synchronization signal has been received and the number of times an abnormal synchronization signal has been detected are cumulatively retained or deleted according to a predetermined multiplication factor to provide redundancy that protects from immediately linking a determination of a coincidence to an output, and to provide a redundancy that protects the number of times an abnormal synchronization signal has been detected and the number of times an abnormal synchronization signal has been detected. It was decided whether synchronization was established or lost based on the ratio of the number of times the synchronization was performed, and the result was output as a signal.

Devices that implement this method include a code identification unit 11 that identifies whether an input signal is a synchronization code, and an update count for cumulatively retaining or deleting retained normal or abnormal synchronization signals according to a predetermined multiplier. It has a control unit 12, a synchronization number holding means 13a for holding the number of times a normal synchronization code has been received, and an asynchronous number holding means 13b for holding the number of times an abnormal synchronization signal has been detected. It is provided with a protection section 13 that provides redundancy to protect the determination from being immediately linked to the output of the result, and an output section 14 that outputs whether or not synchronization has been established based on the output signal from the protection section 13.

The synchronous number holding means 13a and the asynchronous number holding means 13b provided in the protection part 13 may be formed by the same means each defined by an on state and an off state.

In this case, as shown in the embodiment diagram of FIG. 2, it is preferable that the frequency update control section 12 is formed by a shift clock generation section 22 and the protection section 13 is formed using a bidirectional shift register 23a.

[Effect]

With the above configuration, the present invention checks whether the input signal is a synchronous code by the code identification unit 11, and if it is a synchronous code, the protection unit 1
The number of receptions of the synchronization code is held in the synchronization number holding means 13a of No. 3 in accordance with the specification of the number update control section 12, and the number of reception times of the synchronization code is stored in the asynchronous number holding means 13b of the protection section 13 if it is not a synchronization signal. It is held according to the specification, and even if it coincidentally matches the synchronization code, the matching result is not immediately output, but it is determined according to a predetermined ratio of abnormality and normality, and the determination result is output from the output section 14.

Further, if the synchronization number holding means 13a and the asynchronous number holding means 13b are formed by the same means defined by the on state and off state, the number of times of synchronization code reception can be specified by the number update control unit 12. It is turned on by multiplying it by a multiplier, and turned off by multiplying it by a specified multiplier than the number of times it is not a synchronization code, and the determination is made based on the predetermined number of on-states.

In addition, the number update control unit 12 is shifted to the clock generation unit 22.
In the case where the protection unit 13 is formed by a bidirectional shift register 23a, the bidirectional shift register 23a is shifted to the right by multiplying the number of clocks by the number of times the synchronization code is received, or if the code is not a synchronization code. The signal is shifted to the left by multiplying the number of clocks by the number of clocks, and the determination is made based on the output signal output from a specified output terminal.

〔Example 〕

Hereinafter, as an embodiment of the present invention, a case where a bidirectional shift register is used will be illustrated and explained.

FIG. 2 shows the configuration of the embodiment device.

Here, 21 is a code identification unit that checks the input signal and outputs a high level signal if the signal is a synchronous bit that is sent every 193 bits, and outputs a low level signal if it is not a synchronous bit. It has a synchronization code identification circuit 21a that outputs a signal at a level, and a NOT circuit 21b that inverts the output signal from the synchronization code identification circuit 21a and outputs it as a control signal to shift it to the left.

Reference numeral 22 denotes a shift clock generating section, which generates a clock signal for bit shifting according to the judgment result of the synchronization code.
1 if synchronization is normal, 2 if synchronization is abnormal
Outputs two pulse signals.

23 is a protection unit, which includes a bidirectional shift register 23a that inputs a synchronous bit and shifts it to the right, and inputs an asynchronous bit and shifts it to the left, and outputs an output signal from the Q1 output terminal and from the Q2 output terminal. The output signal of NOT circuit 23b
Based on the inverted signal, it is determined whether synchronization is established or not.

24 is an output unit which inputs the two output signals of the protection unit 23 and outputs a signal at a high level when synchronization is established;
If synchronization is lost, a low level signal is output.

The shift clock generating section 22 generates a clock signal CLOCK.
A which inputs the clock signal 2CLK with twice the frequency of the clock signal CLOCK and outputs their logical product.
An ND circuit 22a, an AND circuit 22b which inputs the output signal of the AND circuit 22a and the output signal of the synchronization code identification circuit 21a and outputs their AND, and a clock signal C.
An AND circuit 22c inputs the output signals of the LOCK and NOT circuits 21b and outputs their AND, and an OR circuit 22d inputs the Ryokawa power signals of the AND circuits 22b and 22c and outputs their logical sum. Be prepared.

The protection unit 23 has eight output terminals from Q to Q8 whose initial state is all low level (all 0) (shift register 5N7419 manufactured by Texas Instruments).
The bidirectional shift register 23a includes a bidirectional shift register 23a (such as SHIFT RIGH) and a NOT circuit 23b that inverts and outputs the output signal from the Q2 output terminal of the bidirectional shift register 23a.
T) Input the output signal of the synchronization code identification circuit 21a to the input terminal, input the output signal of the NOT circuit 21b to the left shift (St (IFT LEFT) input terminal, and input the output signal of the NOT circuit 21b to the clock (CL) input terminal.
The output signal from the shift clock generating section 22 is input to the OCK) input terminal, and the signal is output from the Q1 output terminal and the Q2 output terminal to the output section 24 side.

The output section 24 includes a NAND circuit 24a that receives an output signal from the NOT circuit 23b, and a bidirectional shift register 23.
An output circuit consisting of a NAND circuit 24b to which the output signal from the Q1 output terminal of a is input is formed. NAND circuit 2
In addition to the output signal of the NOT circuit 21b, the output signal of the NAND circuit 24b is input to 4a, and a signal obtained by inverting the logical product of these is output. In addition to the output signal from the Q□ output terminal of the bidirectional shift register 23a, the output signal of the NAND circuit 24a is input to the NAND circuit 24b, and a signal obtained by inverting their AND is output.

In the embodiment configured in this way, the code identification unit 21 receives one bit for every 193 bits of the transmitted signal.
is input. Depending on whether the signal is a synchronization bit or not, a high level signal is output from the synchronization code identifying circuit 21a if it is a synchronization bit, and a low level signal is output if it is not a synchronization bit.

When a high level signal is output from the synchronization code identification circuit 21a (synchronization is OK), the bidirectional shift register 23
A high level signal is input to the right shift input terminal of Q1, and one pulse signal is output from the shift clock generating section 22, inputted to the clock input terminal, shifted to the right by 1 bit, and then output from the Q1 output terminal. A high level signal is output.

The subsequently output signal is also a high level signal (synchronization OK)
In the case of , it is similarly shifted to the right by 1 bit,
A high level signal is output from the Q, , Q2 output terminals.

These output signals are sent to the output section 24, the signal from the Q1 output terminal is input to the NAND circuit 24b, and the signal from the Q2 output terminal is input to the NAND circuit 24b.
A signal from the output terminal is input to the NAND circuit 24a, a high level signal is output from the NAND circuit 24a, and synchronization bits are detected consecutively (twice in the illustrated example), so synchronization is established.

When a low level signal is output from the synchronization code identification circuit 21a (synchronization NG), the bidirectional shift register 23
A high-level signal is input to the left shift input terminal of a through the NOT circuit 21b, and two pulse signals are output from the shift clock generator 22 and input to the clock input terminal, and are shifted to the left by 2 bits. Q8. Q
, the output from the output terminal becomes a low level signal.

If the subsequently output signal is a low level signal (synchronization NG), it is similarly shifted to the left by 2 bits, and the outputs from the two output terminals with smaller numbers than the previous time become low level signals. Through this repetition, when an asynchronous bit is detected, the Q output terminals change to low level output two by two in order from the one with the highest number (in the illustrated example, it is repeated up to four times cumulatively), and all outputs are When the output signal from the terminal becomes low level (even the Q1 output terminal becomes low level), the NAND circuit 24 of the output section 24
The signal output from a becomes low level, resulting in loss of synchronization.

Furthermore, when the signal output from the synchronization code identification circuit 21a is a high level signal and a low level signal at random, the right shift is 1 bit at a time, while the left shift is 2 bits at a time. , the protection unit 23 detects asynchronous bits rather than consecutively detecting synchronous bits.
It is faster if all the signals output from the are at low level,
Out-of-sync is easily detected.

In this example, the ratio between synchronization establishment and synchronization loss is set to 1/4 to make it easier to detect synchronization loss, so that when synchronization is lost, a signal coincidentally coincident with the synchronization bit is received. Even in such cases, out-of-synchronization can be easily detected, and time loss caused by undetected out-of-synchronization can be reduced.

It should be noted that the above-mentioned examples are specifically described in order to better understand the gist of the present invention, and unless otherwise specified,
This does not limit other embodiments.

For example, in the illustrated example, the number of times is four, but the number of conditions for detecting out of synchronization may be increased (more than four times) in order to make it more difficult to detect out of synchronization.

〔Effect of the invention 〕

As described above, the present invention identifies whether an input signal is a synchronization code or not, and cumulatively stores or deletes the number of times a normal synchronization code is received and the number of times an abnormal synchronization signal is detected according to a predetermined multiplier. synchronization, which provides redundancy to protect judgments on coincidences from being immediately linked to the output, and determines whether synchronization is established or out of synchronization depending on the ratio of these retained times, and outputs the result as a signal. By using this as a protection method, synchronization errors can be detected even when synchronization codes and non-synchronization codes, which could not be detected in the past, are repeated alternately, eliminating time loss caused by undetected synchronization errors for a long time. can.

Further, if the input signal checked by the code identification unit 11 is a synchronous code, the synchronization protection circuit receives the input signal from the synchronization count holding means 13a.
If it is not a synchronous signal, the asynchronous number holding means 13b,
The number of reception times is multiplied by a multiplier specified by the number update control unit 12 and held, so that even if the synchronization code coincidentally matches, the matching result is not immediately outputted to provide redundancy, and a predetermined abnormality and normality are maintained. By outputting the judgment results according to the ratio of
Unnecessary waiting time can be reduced and processing time can be shortened.

Further, the synchronization number holding means 13a and the asynchronous number holding means 13b are formed by the same means defined by the on state and the off state, and are turned on at a specified times the number of times the synchronization code is received according to the designation of the number update control unit 12, or Turn off the specified times the number of times the code was not a synchronization code,
By making the determination based on the predetermined number of on-states, the configuration can be simplified and costs can be reduced.

Also, the number update control section 12 is made into a shift clock generation section 22, and the protection section 13 is made into a bidirectional shift register 2.
3a, and according to the specified number of clocks, the bidirectional shift register 23a is shifted to the right by multiplying the number of clocks by the number of times the synchronization code was received, or shifted to the left by multiplying the number of clocks by the number of times the synchronization code was not received. By outputting the determination result from a specified output terminal, parts procurement becomes easier, the configuration can be further simplified, and costs can be reduced.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the principle of the present invention; Figure 2 is a diagram showing a synchronization protection circuit according to an embodiment; Figure 3 is a diagram showing a conventional synchronization protection circuit; and Figure 4 is a synchronization code. FIG. 3 is an explanatory diagram of input/output signals in the identification circuit. 11... Code identification section 12... Number update control section 13... Protection section 13a... Synchronous number holding means 13b... Asynchronous number holding means 14... Output section 22... Shift clock generation Section 23a...bidirectional shift register Fig. 1

Claims (4)

[Claims] (1) Identify whether the input signal is a synchronization code or not, and cumulatively retain or delete the number of times a normal synchronization code was received and the number of times an abnormal synchronization signal was detected according to a predetermined multiplier. It is characterized in that it provides redundancy to protect the determination of coincidence from being immediately linked to the output, and also determines whether synchronization is established or loses synchronization based on the ratio of the number of times the synchronization is retained, and outputs the result as a signal. Synchronization protection method. (2) A code identification unit (11) that identifies whether an input signal is a synchronization code; and a number update control unit (12) that cumulatively retains or deletes normal or abnormal synchronization signals held according to a predetermined multiplier. ), a synchronization number holding means (13a) for holding the number of times a normal synchronization code has been received, and an asynchronous number holding means (13b) for holding the number of times an abnormal synchronization signal has been detected. A protection section (13
) and an output section (14) that outputs whether or not synchronization is established based on the output signal from the protection section (13). (3) Synchronization count holding means (
3. The synchronization protection circuit according to claim 2, wherein the asynchronous number holding means (13a) and the asynchronous number holding means (13b) are formed by the same means each defined by an on state and an off state. (4) The number update control section (12) is a shift clock generation section (22), and the protection section (13) is formed using a bidirectional shift register (23a). Synchronous protection circuit.