JPS62188442A - Counter circuit - Google Patents

Abstract

PURPOSE:To shorten the alarm sending time by providing a flip-flop circuit inputting the output of content of other counter of a counter circuit as a data input, inputting the output of the 1st timer circuit as a clock input and outputting an alarm. CONSTITUTION:A counter circuit 11 counts an error pulse 101, its output state is changed when the predetermined under of pulses of above is counted and the content of counter is cleared by using a pulse 103 from a timer circuit 2. The output state of the counter circuit 11 is stored in flip-flop circuits 12-15 constituting a shift register by using a pulse 103 of the timer circuit 2. When the number of error pulses is (k) or below, the output of the counter circuit 11 is at an L level and when the number of pulses is (k) or above, the output is at an H level, and when the state that error pulses of (k) or above in a prescribed time T' takes place four times consecutively, an L level is outputted in a NAND gate 16. If the state does not take place four times consecutively, the NAND gate 16 is at an H level. Thus, the alarm generating time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counting circuit, and particularly to a counting circuit that monitors the error state of a transmission line by counting error pulses when monitoring errors occurring in the transmission line.

[Conventional technology]

As a method for counting error pulses in a transmission path, there is a method in which more than one cycle of error pulses is counted during a certain period of time T, and a blue alarm signal is generated when this state continues N times. Here, the values of T and N are derived from the assumed probability of error occurrence on the transmission path.

If it is incorrect, it can be calculated assuming that it follows the Boisson distribution.

Occur. The counter circuit 52 counts the error pulses 101 during a certain period of time 'r, and the repulse 101 is counted by the timer circuit 51.
Each time 09 is supplied, the count contents are erased. When counting error pulses during a certain period of time T, the state of the output signal 110 of the counter circuit 52 changes and its state Fi
Hold Af. The 8-stage shift register circuit 53 is connected to the timer circuit 51);
The output signal 1107 of 2; is shifted. Nantes Gate 5
4 constitutes the logic circuit of the output signal of each stage of the shift register circuit 53, and when the counter circuit 52 consecutively counts N or more error pulses during a certain period of time T, an alarm signal 111 is generated. Send out.

[Problems that the invention attempts to solve]

In this conventional example, a shift register circuit 53 of NN
The shift register circuit 53 shifts and stores one output of the pulse counter circuit 52 for a certain period of time 'r supplied from the timer circuit 51. It takes N times T to send out the alarm signal. In particular, if the error rate of the transmission line to be monitored is reduced, the constant time T required to count the number of error pulses will become longer, and it will take more time to send out an alarm, and the transmission line for switching the transmission line will become longer. When used for error monitoring, there is a drawback that switching time becomes long.

[Means for solving problems]

The counting circuit of the present invention includes a first timer circuit having a first period, a second timer circuit longer than the first period, an error pulse as input, and counter contents can be input from the outside. It is equipped with a data input terminal 8, an input control terminal, a terminal on the counter content erasing side (to), and two counter content output terminals, and outputs the output of the first timer circuit among the timer circuits to both terminals on the counter content erasing side. A counter circuit as an input, and a memory that receives the counter content output of one of the counter circuits as an input, stores the counter content in synchronization with the output of the second timer circuit, and inputs the output to the data input terminal of the counter circuit. a burst error detection circuit that receives the error pulse as input, detects a burst error in the transmission line in synchronization with the second timer circuit, and inputs an output to the data input control terminal of the counter circuit; and the counter circuit. and a flip-flop circuit that uses the output of the other counter as a data input, uses the output of the first timer circuit as a clock input, and outputs an alarm.

〔Example〕

The present invention will be briefly described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. The timer circuit 1 is configured to monitor the error rate l and the required fixed time T.
The timer circuit 2 supplies pulses 102 with an interval of 4, and the timer circuit 2 supplies pulses 103 with an interval of a constant 4 times T', which is shorter than T, in order to prevent alarm output due to the occurrence of a burst error. 3 is error pulse 1
01 and can output the counter contents, and if it counts more than a predetermined number of error pulses, the output state can be maintained, and the counter contents can be cleared by external control. It has a function that allows the contents of the counter to be set externally using a control signal from the outside. The burst error detection circuit 4 is
- It can be realized by the circuit shown in FIG. 2 as an example. As shown in FIG. 2, the counter circuit 11 counts error pulses 101, and when a predetermined number or more is counted, the output state changes and this state is maintained. Clear. The output state of the counter circuit 11 is stored in seven flip-flop circuits 12 to 15 constituting a shift register in accordance with the pulse 103 of the tie-7 circuit 2. If the number of error pulses is less than 1, the output of the counter circuit 11 is 'L'
If the level is set to ``H'' when the level is equal to or higher than kfB, if a state in which more than
" level is output. If it does not occur four times in a row, the Nantes gate 16 is at the "H" level.

When a burst error occurs, more than k iJ error pulses are counted, and the output 109 of the counter circuit 11 is "L".
level changes to "H" level. During the next fixed period of 4, no error pulse 101 is input due to a burst error. Therefore, the output 109 of the counter circuit 11 becomes the 'L' level.
The output becomes "H". At this time, the output of the Nantes gate 16 is at the "H" level, and the output of the Nantes gate 17 is "H" level.
It is possible to detect a burst error by changing from the H level to the 'L' level. Although the shift register 8 in FIG. 2 has four stages, the number of stages may be one as long as it satisfies n T'< T. The output of the inverter 18 is sent to the Nant gate 17.
This is used to prevent malfunctions at changing points. 1st
The memory circuit 5 shown in the figure stores the counter contents of the counter circuit 3 in synchronization with the timer circuit 2.
This can be realized by the shift register circuit shown in the figure. In Figure 8g3, the counter circuit is assumed to be a binary counter and can indicate the counter contents using 4 bits.

Further, the number of stages of the shift register is made to match the number of stages of the shift register of the burst error detection circuit 4.

The output 107 of the burst error detection circuit 4 in FIG. 1 is input to the data input control terminal of the counter circuit 3. Further, the output 106 of the memory circuit 5 is input to the data input terminal of the counter circuit 3. If a burst error is detected,
Then, the output 107 of the parse error detection circuit 4 becomes L" level. Also, the outputs 104 and 105 of the counter circuit 3 become "L" level.
I-1” level.

Since this counting circuit does not have a shift register like the one shown in FIG.
When the burst error detection circuit detects a burst error, the output of the counter 8 before the detection of the burst error is input again to the counter circuit 3 by the detection output (output that reproduces the burst error), so an alarm is not output. do not have.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which the error counting circuit sends out an alarm when a state of error pulse kllA1 or more occurs N times in a row, and by setting N to 1, the error rate is extremely low. It has the function of shortening the alarm generation time when monitoring a small area, and by being equipped with a burst error detection circuit, it can prevent the generation of alarms due to burst errors.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a block diagram showing the burst error detection circuit in the figure, FIG. 3 is a block diagram showing the memory circuit in FIG. 1, and FIG. 4 is a block diagram of a conventional example. 1.2...Timer circuit, 3.11...
Counter circuit, 4...burst error detection circuit,
5...Memory circuit, 6, 12, 13, 14.1
5.21-37...Flip-flop circuit, 1
6.17... Nantes Gate, 51...
Timer circuit, 52...Counter circuit. Agent: Susumu Uchihara, patent attorney.

Claims (1)

[Claims] A first timer circuit having a first period, a second timer circuit having a second period longer than the first period, and a data input that receives an error pulse and allows counter contents to be input from outside. A counter circuit comprising a terminal, a data input control terminal, a counter content erasure control terminal, and two counter content output terminals, the output of the first timer circuit of the timer circuits being input to the counter content erasure control terminal. , a memory circuit that receives the counter content output of one of the counter circuits as an input, stores the counter content in synchronization with the output of the second timer circuit, and inputs the output to the data input terminal of the counter circuit; a burst error detection circuit that detects burst errors on the transmission line in synchronization with the second timer circuit as an input and inputs the output to the data input control terminal of the counter circuit; A counting circuit comprising: a clip-flop circuit which uses the output of the first timer circuit as a clock input and outputs an alarm.