JP3060040B2 - Line error rate detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line error rate detecting circuit for detecting an error rate of a digital line.

In recent years, optical fibers have been used as transmission lines for digital communication, and the error rate of digital lines has been reduced due to the development of optical technology.

[0003] Such a digital line is also used for data transmission, and a line having a lower error rate is required for data transmission as compared with transmission of an analog voice signal.

[0004] The error rate is monitored by dividing the number of error pulses generated within a certain period of time by the amount of data transmitted during that period. For example, it takes about 1000 seconds to detect an error rate of 10 ⁻⁹ .

In order to maintain the reliability of the digital line, it is necessary to constantly monitor the line error rate and take measures such as line switching when the error rate exceeds a reference error rate. There is a need to constantly detect an error rate and to detect the error rate in a minimum time.

[0006]

2. Description of the Related Art FIG. 5 is a block diagram for explaining a conventional example. In the figure, 17 is an error pulse counter, 21 is a protection circuit for performing a two-stage protection operation, and 33 is a timer for generating timer pulses t1 to tn serving as a reference for determining that the error rate has exceeded a reference value. The generation circuit 61 is a selector for selecting one of the outputs of the timer generation circuit 33.

For example, if the transmission rate of the line is 15 Mbps and an error rate of 10 ^-6 is detected, the error pulse is counted for 1 sec, and the amount of data transmitted between 1 sec is 15 × 10 ^6. If the pulse count value is “15”, the error rate of the line is 15 / (15 × 10 ⁶ ), that is, 10 ⁻⁶ .

Therefore, the timer generating circuit 33 is, for example,
0.01, 0.1, 1, 10, 100, 1000 Sec
In this example, the selector 61 selects a 1Sec pulse.

The error pulse counter 17 counts the error pulses EP in units of 1 sec. When the count reaches “15”, an error detection signal is output and written to the protection circuit 21. Next, the error pulse EP for the next 1 sec is counted, and when the count reaches “15”, an error detection signal is output and written to the protection circuit 21. Here protection circuit 2
Since the number of protection stages in one is two, when an error detection signal is written twice consecutively, it is determined that the error rate has exceeded 10 ^-6 and an alarm signal ALM is output.

[0010]

In the above conventional example, the reference error rate of the line to be monitored is determined, and when the error rate exceeds that value, the alarm signal ALM is issued.
Is output.

Therefore, the alarm signal ALM is generated only when the error rate becomes worse than the set reference value, and the actual error rate of the line in operation cannot be monitored.

For example, if an error rate of 10 ^-6 is set for monitoring, the error pulse E is output at an error rate of 10 ^-7 or less.
Even if P occurs intermittently, the occurrence of the error cannot be detected.

According to the present invention, an error rate of a line is detected by determining at which position of a plurality of monitoring time pulses the error detection signal has occurred, and the error rate is detected in the shortest time. A circuit error rate detection circuit capable of performing the above-mentioned operations is to be realized.

[0014]

FIG. 1 is a block diagram for explaining the principle of the present invention. In the figure, reference numeral 100 is a line error rate detection circuit, 10 is an error pulse counting means for counting an input error pulse EP, and outputting an error detection signal when the count value reaches a predetermined count value. This is protection means for protecting the error detection signal output from the pulse counting means 10 by a predetermined number of stages and outputting the same.
Is a plurality of monitoring time pulses t corresponding to the line error rate.
Monitoring time generating means for generating 1 to tn.

Reference numeral 40 denotes a plurality of monitoring time pulses t1 to t4 generated by the monitoring time generating means 30.
tn is an error detection timing determining means for determining in which area of the time tn the error pulse EP inputted by the error pulse counting means 10 is counted, and an error detection signal is generated when the counted value reaches a predetermined count value. By determining in which region of the plurality of monitoring time pulses t1 to tn the signal output after protection of a predetermined number of stages by the protection means 20 is generated by the monitoring time generation means 30, the line error rates ER1 to ER1 are determined. ERn is detected.

[0016]

For example, in order to detect the quality of a digital line, an error detection such as a parity check is performed, and if an error is detected as a result, an error pulse EP is output.

The error pulse counting means 10 counts the number of the error pulses EP, and a predetermined count, for example,
When the count reaches “15”, an error detection signal is generated and written to the protection means 20.

Since such a line error often occurs intermittently, a case where an error detection signal is output a plurality of times continuously is regarded as an error detection. For example, assuming that the number of protection stages is two, when the error detection signal is first output and written to the protection unit 20 and then the second error detection signal is written continuously, the protection unit 20
Outputs an error detection signal.

The timing of the error detection signal output from the protection means 20 is a plurality of monitoring time pulses t1 to tn.
The line error rates ER1 to ERn can be detected by judging in which region the error has occurred.

Further, a plurality of monitoring time pulses t1 to tn
A reset signal generating circuit 50 for generating a reset signal having a cycle shorter than the shortest cycle pulse of the error pulse counting means. When an error detection signal is output and the reset signal generating circuit 50 is output, an error pulse counting means is provided. 10 and immediately start the operation of counting the error pulses EP in the next cycle, so that the error rates ER1 to ER1 can be shortened in the shortest time.
ERn can be detected.

[0021]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
In the figure, the error pulse counting means 10 described in the principle diagram is composed of a 4-bit counter 11 and an AND circuit (hereinafter referred to as an AND circuit) 12, and the protection means 20 is composed of a protection circuit 21 having two protection stages. The monitoring time generating means 30 includes a timer generating circuit 31 and an OR circuit (hereinafter referred to as an OR circuit) 32
And the error detection timing determination means 40 comprises a ring counter 41 and AND circuits 4A to 4E.

In the above embodiment, the error rate 1
This is an example of detecting 0 ^-5 to 10 ^-9 . When the error pulse EP is counted by the counter 11 and the count value becomes “15”, the outputs of QA to QD become “1”. Is output from the device, and an error detection signal is written to the protection circuit 21.

Next, the counting operation of the next cycle is started.
When the count value of the counter 11 becomes “15” again, the second cycle error detection signal is written to the protection circuit 21.
Since the number of protection stages of the protection circuit 21 is two, the error detection signal is output from the protection circuit 21 when the error detection signal is written twice consecutively.

This error detection signal is supplied to AND circuits 4A to 4A
E is connected to one input terminal and the other input terminal is connected to the output of a ring counter 41 which receives, through an OR circuit 32, a 10 ^-5 to 10 ^-9 timer pulse generated by a timer generation circuit 31. QA to QE are connected in order.

Therefore, the output of the protection circuit 21 and the output QA to QE of the ring counter 41 both become "1".
Only the outputs of the ND circuits 4A to 4E become "1". For example, by lighting a light emitting diode, an error rate can be displayed.

FIG. 3 is a diagram for explaining another embodiment of the present invention. The figure detects an error rate of 10 ^-5 to 10 ^-9 in a minimum necessary time. The difference from the embodiment of FIG. 2 is that when an error detection signal is output, the counter 11 and the ring counter 10 to reset 41
A reset signal generating circuit 50 for generating a ^-4 timer;
An AND circuit 13 for further controlling the reset signal;
A NOR circuit (hereinafter referred to as NOR circuit) 14 and inverters (hereinafter referred to as INV) 15 and 16 are provided.

The protection circuit 21 includes a flip-flop circuit (hereinafter referred to as an FF circuit) 22 and FF circuits 2A to 2E.
And AND circuits 4a to 4e for outputting error detection signals from the FF circuits 2A to 2E.

FIG. 4 is a time chart of another embodiment of the present invention. Hereinafter, the operation of the circuit of FIG. 3 will be described with reference to a time chart. 4 shows an error pulse input to the EP counter 11.

Count value The count value of the counter 11 is shown. Since the counter 11 is controlled to be enabled,
It does not count above "15". (In the figure, "1
(5) of the error pulse EP after counting "5" is not counted. ) Threshold Indicates the output of the AND circuit 12, and outputs “1” when the count value reaches “15”. When the count value is "15", the polarity is inverted at INV15 and input to the enable terminal EN in order to stop the operation of the counter 11 in that state.

10 ^-4 timer reset signal generation circuit 50
^Is a 10 ^-4 timer pulse. 10 ^-6 timer, 10 ^-7 timer Of the 10 ^-5 to 10 ^-9 timer pulses generated by the timer generation circuit 31, only the 10 ^-6 timer and the 10 ^-7 timer are shown. FIG. 4 shows that the error rate is 1
This is an example of 0 ^-7 , where only a 10 ^-6 timer for determining a 10 ^-7 area and a 10 ^-7 timer are shown.

10 ^-7 area This signal is used to determine the error rate output from the ring counter 41. The QC output of the ring counter 41 is 10 ^-6 timer pulses and 10
"1" is output during the ^-7 timer pulse.

The threshold is the first written threshold of the protection one-stage FF circuit 22, and is written by the ^10-4 timer pulse immediately after the threshold becomes "1".
(Indicated by (b) in the figure.) The counter 11 is reset by the same signal, and the counting operation of the next cycle is started.

The output of the protection two-stage FF circuit 22 is input to the AND circuits 4A to 4E, and the output of only the AND circuits 4A to 4E whose output of the ring counter 41 is "1" is "1". Here, since it is 10 ⁻⁷ , only the output of the AND circuit 4C becomes “1”. This signal is input to the FF circuits 2A to 2E, and is output at the ^10-4 timer pulse immediately after the next threshold becomes "1".

10 ^-5 timer to 10 ^-9 timer These are 10 ^-5 to 10 ^-9 timer pulses generated by the timer generation circuit 31. 10 ^-5 area to 10 ^-9 area These are the outputs of the ring counter 41. The outputs QA to QE output "1" while shifting by one stage every time a timer pulse of 10 ^-5 to 10 ^-9 is input. . The error rate is detected by determining in which region the counter 11 has exceeded the threshold value.

Here, the protection one-stage output is "1" at the point (b), which is in the 10 ^-7 region, so that the line error rate is determined to be 10 ^-7 . in this way,
The line error rate can be detected by determining in which timer pulse region the timing at which the threshold has occurred is included.

In FIG. 3, the timer generation circuit 31 and the reset signal generation circuit 50 have different configurations. However, it is needless to say that one counter can be used. Also, 10 ⁻⁴ generated by the reset signal generation circuit 50 is used.
When the count value of the error pulse EP exceeds the threshold, the timer pulse resets the counter 11 to start the operation in the next cycle. However, the timer pulse is not limited to 10 ^-4 and detects the error rate. It is sufficient to use a pulse having a value that is one digit lower than the value and can be output easily from the counter 11.

When the error pulse EP does not reach the threshold, the counter 11 and the ring counter 41 are reset by a 10 ^-9 timer pulse in FIG.

[0038]

According to the present invention, a timer generating circuit for generating a plurality of timer pulses is provided, and the error rate of the line is detected by determining in which timer pulse area the error pulse has exceeded the threshold. be able to.

A reset signal generating circuit for generating a reset signal having a shorter cycle than the shortest timer pulse for detecting a line error rate is provided. When the error pulse exceeds a threshold, the reset signal generating circuit generates the reset signal. By resetting the counter by the reset signal, the operation in the next cycle can be started immediately, and the error rate can be detected in the shortest time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a diagram illustrating another embodiment of the present invention.

FIG. 4 is a time chart of another embodiment of the present invention.

FIG. 5 is a block diagram illustrating a conventional example.

[Explanation of symbols]

REFERENCE SIGNS LIST 100 Line error rate detection circuit 10 Error pulse counting means 11 Counter 17 Error pulse counter 12, 13, 4A-4E, 4a-4e AND circuit 14 NOR circuit 15, 16 I
NV 20 protection means 21 protection circuit 22, 2A to 2E FF circuit 30 monitoring time generation means 31, 33 timer generation circuit 32 OR circuit 40 error detection timing determination means 41 ring counter 50 reset signal generation circuit 61 selector

Claims (2)

(57) [Claims] 1. A circuit for detecting an error rate of a digital line, comprising: an error pulse counting means (10) for counting input error pulses (EP) and outputting an error detection signal when a predetermined count value is reached. A protection means (20) for protecting the error detection signal output from the error pulse counting means (10) by a predetermined number of stages and outputting the same, and a plurality of monitoring time pulses (t) corresponding to the line error rate.
Monitoring time generating means (30) for generating monitoring time pulses (t1 to tn) generated by the monitoring time generating means (30);
n) an error detection timing judging means (40) for judging in which area the error pulse (EP) inputted by the error pulse counting means (10) is counted. When reaching the numerical value, a signal output by protecting the error detection signal with the protection means (20) is output to the monitoring time generation means (30).
A line error rate detection circuit for detecting a line error rate (ER1 to ERn) by judging in which region of a plurality of monitoring time pulses (t1 to tn) that occur. 2. A circuit error rate detection circuit according to claim 1, wherein said error pulse counting means (10) counts the number of error pulses (EP) input, and reaches a predetermined count value to output an error detection signal. Sometimes, the error pulse counting means (1
A reset signal generating circuit (50) for generating a reset signal for resetting 0) is provided, the error pulse (EP) input by the error pulse counting means (10) is counted, and an error detection signal is output when a predetermined count value is reached. And when the reset signal generation circuit generates a reset signal, the error pulse counting means is reset to start an error detection operation in the next cycle. The described line error rate detection circuit.