JPS58111758A - Trigger circuit - Google Patents

Abstract

PURPOSE:To generate a trigger signal detecting missing and delay of a signal to be measured by a method wherein an AND signal between a signal meeting requirement and a clock signal is counted and reset with the signal being measured, where the counts are compared with a set value. CONSTITUTION:Information switching sections 2, 5 and 13 are turned to the positive position and a clock selector 12 of a clock switching section 14 is connected to an external clock EXC. A detection count setting section 17 sets (n) and generates 18 a setting signal. The set value (n) is set at a latch memory 16 and a count stating memory 3 and a counter 7 are cleared. An input buffer section 1 outputs a signal CS from among trigger requirement signals ARM. Subject to the signal CS, a memory 3 provides a signal CE to an AND circuit 15, to the other terminal of which a signal EXC is applied to actuate the counter 7. When a signal SSG to be measured is generated in an input buffer section 4, the memory 3 and the counter 7 are cleared. The count (m) outputted to a comparator 19 is compared with the value (n) in the memory 16 and the comparator outputs a trigger signal TRG.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a trigger circuit for a waveform observation device g for performing waveform monitoring of a digital signal, for example.

A memorized waveform observation device is used to measure the waveform m side of the digital signal, and this device includes a trigger circuit for prompting a signal for visual observation.

Conventional trigger circuits of this type monitor single or multiple signal states, and when specific conditions set by the observer are met, a trigger signal is generated, and the measured signal is memorized and re-pressured. It is something to do.

That is, Figures 1 and 2 show the configuration diagrams of conventional trigger circuits.In Figure 1, channels from ch+ to c
hn is an input terminal to which the signals under test 1 to n are respectively input;
Each terminal Ch+~chn is a comparator cp+~CT, respectively.
) n, and each comparator Cp1 to Cpn
The other end is connected to level setting switches F-IJ1 to LEn. Further, the output sides of Cpj to cpn are connected to the input terminal of an AND circuit AND via selection switches SE and 5EnY, respectively. Each comparator cp1 to cpn
compares the input signal with the level power setting 1i[, outputs the logic signal 111y with the input signal 1H1, and selects the 1 selection switch SE.
When the conditions of all the channels of the turned-on switches among channels 1 to SEn are satisfied, the AND circuit A generates a trigger signal and outputs it to a durability circuit (not shown). □ The circuit shown in Figure 2 is an OR circuit instead of an AND circuit. rOR is used% and each comparator cp1
~cpn outputs logic 11 at input signal "Ll". Therefore, this circuit has 1 selection switch SE1
-SEn, when any of the channels of the turned-on selection switch satisfies the condition, a trigger signal is generated from the OR times %OR and is output to a storage circuit (not shown). As mentioned above, the trigger generation in the conventional trigger circuit is 1
It is only generated when certain selected conditions are met, so if a signal that is expected to occur at a certain point does not occur, it is impossible to detect and observe it.
It is P. This means that it is not possible to watch the play 11 in which the waveform signal, which is generated periodically at regular intervals, is missing for some reason or the interval is abnormally long.

Especially lately? ] In a miscellaneous digital circuit, it is not a persimmon that the signal that should be generated periodically does not appear, or the interval becomes abnormally large, causing malfunction of the entire device. It has been extremely difficult to determine the cause of a problem using a waveform observation device having a conventional trigger circuit.

The present invention has been developed in view of the above, and its purpose is to detect the occurrence of a signal that is generated periodically at a constant interval of kW or when the interval becomes abnormally good. DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention, which aims to provide a trigger circuit that detects and generates a trigger signal, will be described in detail below with reference to the figures.

FIG. 3 is a circuit diagram showing an embodiment of the present invention. The part surrounded by a dotted line is a trigger circuit, which is set as a condition for a certain signal and takes a certain period of time (a certain number of clocks) from the generation of this signal A. In a circuit in which another signal B is expected to be generated later,
This rule prevents signal B from being dropped. In the same figure, 1 is the first input buffer section, which is the pre-stage trigger condition signal A.
When RM is input, a command from the information switching section 2 of @1 detects a change in the rising edge (positive) of the signal or (negative) if the falling edge of the signal is to be given meaning and outputs a signal C8t.

Reference numeral 3 designates a count start memory. This memory 3 is an edge trigger type memory, which outputs a signal Cm when it receives a -carrier C8, and maintains that state until it receives a signal CR next time.

4 is the input buffer section of 8g2, and this buffer section 4 is also 1
According to the command from the l1n IC second information switching unit 5,
It is detected that the signal change of the II foot signal 8SG has changed to the positive 11111 or negative side, and outputs it to the count start memory 3 and the counter 7 as a reset signal CR through the OR circuit 6.

9 is a clock generator, and a clock cycle setting section 10
A clock signal IC is output based on the set frequency TCK.

Reference numeral 11 denotes an input buffer section of H3, which receives an external clock signal KXC'i and outputs a signal ECi to the input terminal of the clock selector 12. Reference numeral 13 denotes a third notification alarm section, which sends a change detection signal to the clock generator 9 and input buffer section 11.

Gives a negative setting bias. The clock selector 12 is.

Based on the command of the clock switching unit 14, the input internal clock IC, y, or external clock EC' is selected and the signal CL is output. 15 is an AND circuit, which connects signals CE and O.
A logical AND signal with L is outputted to the counter 7Il'r, and the counter 7 counts the number of input pulses until the reset signal CR is applied. 16 is a latch memory for storing the detection count (set value nv from the installation foot 17), and 18 is a set signal generating section.

Give a set signal to the latch memory 16, and! Also, the count start memory 3 and the counter '
Give a clear signal to 7. , 19 is a comparator, and this comparator 19 is set to 11■n Y B, and when the count f[E ffl Y A of the counter 7 is set, the trigger signal TRG is sent to the memory circuit for waveform observation under the condition of A>B. Output.

The operation of the present invention configured as described below will be explained. First of all, from the generation of the condition signal ARM to the signal under test S
The case where the interval until the generation of SG is given by the number of external clocks will be explained with reference to FIG.

1st~! 1 information switching unit 2.5.13'ik - each positive 1
41+1 (-1-1), and the clock selector 12Y external clock gXc'
Connect 1llHc. Further, the detection count setting section 17 sets n, and the set signal generating section 18 generates a set signal. As a result, the latch memory 16 is set to 111.
n is set, and count start memory 3 and counter 7 are cleared by signals input via OR circuit 6, respectively. In this state, when the pre-stage trigger condition signal ARM is input at 1 o'clock, the input buffer section 1 detects the J7 signal of the signal ARM and outputs CB. The count start memory 3 continues to output the signal CF to the input terminal of the AND circuit 15 under the condition of the signal CB.

On the other hand, and episode 111i! The external clock signal EXC is input to the other input terminal of the buffer section 11.15. Since it is input as the clock signal CL via the clock selector 12, the AND condition is satisfied in the AND circuit 15, and the counter 1
1 and counting starts. When the signal under test SSG is generated after n clocks at time t2, the input buffer section 4 detects its rising edge and generates the signals C, PL, and the counter start memory 3 and counter 7 are cleared respectively.

Count output to comparator 19 &Z
Since the e-electric value does not exceed n, the trigger < q TRG
is not output. However, as shown by the dot in Figure 4, the measured signal 88 that should be generated after n of the clock HCXC decoding.
If G does not occur, the counter 7 continues counting, and the comparator 19 outputs a trigger signal at time t3 at the moment when the count 100 exceeds the set 1 tooth n by 0.

Next, as a second measurement method, from the generation of the signal ARM to the signal S
The case where the interval until the occurrence of SG is given by time will be explained using FIG. 5.

In this case, after the first condition signal ARM is generated, the signal under test S
Since the interval until the SG is emitted is determined by time, the clock frequency setting section 10 sets the period to 'rC time, and the clock switching section
2 internal clock IC11111. And the time from generation of signal ARM to generation of signal SSG! Assuming T, the set count value n of the detection count value setting section 14 is calculated from these Tc and T as follows.

However, α is the number of electric currents determined according to the accuracy of time T, and after determining the setting @n in this way, it is decided to output the set signal from the set signal generator 1B, as explained in Fig. 44. This method can be used to detect missing or abnormally delayed signals in the measured signal. It should be noted that the signal SSG is lost at time t2, and it is detected and the trigger signal TRG'1 is generated at time t4.
The delay time Td until the % output is one clock of the external clock BXC in the case of FIG.
In the case of the figure, it is α clock of the maximum internal clock IC.

α is a value of 1 or more, and it is necessary to select an appropriate value according to the accuracy of the given time interval, but if the interval time is given with a sufficiently high precision, the spear will be T
By making c and α small and n large, Td can be made small, and 2. I am fascinated by the fact that I can obtain a trigger signal with a fast response.

Next, as a third measurement method, an example of application in the case where the generation of signals ARM and 88G has repeatability will be explained using FIG. 6. In this case, the time from the signal ARM generation to the signal SSG generation tube (-) can be set either internally or externally, but the setting corresponding to 1 time t1 to t2 is the detection count + 1 as in the above-mentioned example. When the signal 88G is missing at the time t3 when the signal 88G is set by the setting unit 17[, the trigger signal is outputted at the time t4 by the same circuit operation.

As described below, the present invention provides a digital circuit with one time period (fixed number of clocks) f &
As a means of generating a trigger signal when a signal that is predicted to be generated is missing for some reason, a latch memory f3 is stored in advance and the logic between the condition fulfillment signal and the clock signal is stored. The product signal is counted by a counter, the counter is reset by the signal to be measured, and this count value is compared with the set value by a comparator, and a trigger signal is output when an abnormality occurs. Therefore, if the present invention is applied to a trigger circuit of a waveform observation device, for example,
Phenomena that are difficult to observe with existing waveform observation equipment are likely to occur.

The scope of use of one device can be greatly expanded.

In addition, since conventional waveform observation equipment uses a method to generate a trigger from a phenomenon that occurs at the time of engineering, if a signal is lost for some reason, the phenomenon cannot be detected and one circuit Great time for testing and troubleshooting! had to spend. In this regard, in the present invention, since a trigonometric signal is generated when a signal is lost, there are significant advantages such as the time required to investigate the cause of a trouble is greatly shortened.

[Brief explanation of the drawing]

Figures 1 and 2 are block diagrams of a conventional trigger circuit, Figure 3 is a circuit diagram showing an embodiment of the present invention, and Figures 4, 5, and 6 respectively explain the present invention. FIG. 1.4.11 are manual buffer sections, 3 is a count start memory, 7 is a counter, 9 is a clock generator, 1
6 is a latch memory, 19 is a combiner. 5 Figure 3

Claims (1)

[Claims] A device that generates a trigger signal detects the absence or delay of the signal under test that occurs after a certain period of time after the generation of a signal where a specific condition is met, and outputs the input of the signal where the condition is met. and a count start memory which is reset by the generation of the complementary signal under test, and an AND signal of the output signal from this count start memory and the clock signal, which is reset by one signal under test. counter and e? from lfa output count box setting section?
It is equipped with a latch memory that stores a double signal, and a comparator that outputs a trigger signal when the setting 1 stored in this latch memory (compares u with the count value of the counter and selects a value from the set value) Ill becomes large. A trigger circuit characterized by: