JPH05199209A - Error detecting circuit - Google Patents

Abstract

PURPOSE:To output an alarm signal in short detecting time when an error ratio is made adverse by outputting the alarm signal from a protecting means when an error detecting signal to be outputted by an error detecting means when a count value exceeds a prescribed value, continues a second prescribed value. CONSTITUTION:Plural timing signals in various cycles are generated by a timing generating means 20, one of those signals is selected by a selecting means 60, the number of error pulses inputted in this signal is counted by an error count means 10, and the output is inputted to an error detecting means 30. When the output of the means 10 is turned to the first prescribed value, the error detecting signal is outputted from the means 30. This signal is inputted to an alarm monitor means 50, ANDed with the closest timing signal among the plural timing signals outputted by the means 20, and inputted to an OR means 70, the error detecting signal outputted from the means 30 is written in a protecting means 40 by this output, and an initial value is loaded to the means 20. Thus, error detecting time is shortened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error detection circuit for detecting a line error in a digital line. In recent years, an optical fiber has come to be used as a transmission line for digital communication, and line errors have been reduced due to the progress of optical technology.

Generally, a long monitoring time is required to detect such a low line error, but in order to maintain a high line quality, the line is switched when the line error increases. In order to take measures such as the above, it is necessary to detect an increase in line error in as short a time as possible and output an alarm signal.

[0003]

2. Description of the Related Art FIG. 5 shows a diagram for explaining a conventional example. In the figure, 11 is a counter, 22 is a timing generation counter, and 3
1 is a NOR circuit (hereinafter referred to as NOR circuit), 41
Is a flip-flop circuit (hereinafter referred to as FF circuit), 6
1, 62 and 63 are AND circuits (hereinafter referred to as AND circuits), 64 is a logical sum circuit (hereinafter referred to as OR circuits), 7
2 is a delay circuit.

The figure shows an example of outputting an alarm signal (indicated as an ALM signal in the figure) in the first stage of protection when four error pulses are input. In the figure, the timing generation counter 22 has a cycle of 1 Se for counting error pulses.
c, 10 Sec, and 100 Sec, three kinds of timing signals are generated. The three types of timing signals are input to the AND circuits 61 to 63, respectively, and the timing signal in which the threshold setting signal is set to H is output through the OR circuit 64.

On the other hand, the number of input error pulses is counted by the counter 11, and its output is input to the NOR circuit 31. The outputs QA and QB of the counter 11 are input with the same polarities, and the polarities of QC are inverted and input. Therefore, when the QA and QB are "0" and the QC is "1", the NOR circuit 31 outputs "1". That is, when four error pulses are input, the error detection signal “1” is input to the FF circuit 41.

The error detection signal "1" of the NOR circuit 31 is input to the enable terminal EN of the counter 11 to stop the operation of the counter 11. Here, when “1” is output from the output of the OR circuit 64, the FF circuit 4 outputs this output.
The alarm signal (indicated by ALM in the figure) is output by 1 and the counter 11 is cleared by the delayed output by the delay circuit 72.

FIG. 6 shows a time chart of a conventional example. It is a timing signal with a short cycle output from the timing generation counter 22.

This is a timing signal with a long cycle output from the timing generation counter 22. The error pulse input to the counter 11 is shown. At this time, the number of detected error pulses exceeds 4, so NO
The R circuit 31 outputs the output “1”.

Normally, since a timing signal having a long cycle is set as the timing signal, the NOR circuit 31 detects an error and holds it as it is, and outputs an alarm signal when the timing signal is input.

[0010]

In the above-mentioned conventional example, the counter 11 counts error pulses, and when the number of error pulses reaches a specified number, here four, NO is reached.
Although the error detection signal is output from the R circuit 31, the output is held as it is and the timing generation counter 22
The alarm signal is output from the FF circuit 41 at the time point when the timing signal output by is input.

In a line using an optical fiber these days, the line error rate is becoming low, and it takes a long time to monitor an error occurring at a low frequency. For example, from several tens of seconds to several minutes. In some cases, it is a monitoring cycle.

In FIG. 6, even if the NOR circuit 31 outputs the error detection signal, it cannot output the alarm signal until the timing signal is input, but the alarm signal can be output by the timing signal. If possible, it is possible to output the alarm signal by α shown in the figure at an early timing.

The present invention intends to realize an error detection circuit capable of outputting an alarm signal in a short detection time when the error rate deteriorates while monitoring the error rate of a line by a timing signal having a long cycle. To do.

[0014]

FIG. 1 is a block diagram for explaining the principle of the present invention. Reference numeral 10 in the figure is an error counting means for counting the input error pulse, and 20
Is a timing generating means for generating a plurality of timing signals for the error counting means 10 to count the error pulses, and 30 detects that the count value of the error counting means 10 exceeds the first predetermined value. An error number detecting means for outputting an error detecting signal, and 40 is a protecting means for detecting that the error detecting signal output by the error number detecting means 30 has continued a second predetermined value and outputting an alarm signal. ..

Further, reference numeral 50 is an alarm monitor for taking a logical product with the closest timing signal of the plurality of timing signals generated by the timing generation means 20 when the error detection signal is output from the error number detection means 30. Reference numeral 60 is a selecting means for selecting and outputting one of the plurality of timing signals generated by the timing generating means 20, and 70 is an output of the alarm monitoring means 50 and a selecting means 6.
The error count detecting means 30 detects the fact that the number of error pulses exceeds the first predetermined value, and outputs the error of the error count signal of the error counting means 10 by the logical sum means. The counting operation is stopped, the error counting means 10 is reset by the output of the logical sum means 70, and then the counting of the error pulse is restarted.

[0016]

The timing generating means 20 generates a plurality of timing signals having different periods, the selecting means 60 selects one of the timing signals and outputs the selected timing signal. The counting means 10 counts and the output is input to the error number detecting means 30.

The error number detecting means 30 has a first reference serving as a reference for determining that the error rate of the line has deteriorated.
When the output of the error count means 10 reaches the first predetermined value, the number of error pulses reaches the first predetermined value from the error number detection means 30. An error detection signal indicating that is output.

This error detection signal is sent to the alarm monitoring means 5
0, the logical product of the closest timing signal among the plurality of timing signals output from the timing generation means 20 is calculated, and the logical product is input to the logical sum means 70. This output is the output of the error number detection means 30. While writing an error detection signal to the protection means 40, the timing generation means 20
Load the initial value into.

When the error pulse does not exceed the first predetermined value, the timing signal selected by the selecting means 60 is used to load the initial value into the timing generating means 20, and the error pulse is set to the first value. The fact that the predetermined value is not exceeded is written in the protection means 40, the error counting means 10 is reset, and the error counting operation is restarted.

By such an operation, when the output of the error count means 10 exceeds the first predetermined value, the alarm signal can be output with the earliest timing signal among the plurality of timing signals. The error detection time can be shortened.

[0021]

FIG. 2 is a diagram for explaining an embodiment of the present invention.
Reference numeral 11 in the figure is a counter as the error error counting means 10 described in the principle diagram, and 21 is a timing generating means 20.
, 31 is a NOR circuit as the error number detecting means 30, 41 is an FF circuit as the protecting means 40, and 51 is an AND circuit as the alarm monitoring means 50.

Further, the AND circuits 61 to 63 and the OR circuit 64 compose the selecting means 60, and the OR circuit 71 and the delay circuit 72 compose the logical sum means 70. The NOR circuit 31 in this embodiment is set to detect the error pulse "4", and the timing generation counter 21 is set to 1 Se.
In this example, three timing signals of c, 10 Sec and 100 Sec are generated and the number of protection stages is one.

FIG. 3 is a time chart of the embodiment of the present invention. The numbers in the time chart indicate the signal waveforms at the points added to the embodiment of FIG. The operation of the embodiment of FIG. 2 will be described with reference to the time chart of FIG.

This is an error pulse input to the EP counter 11. a Shows the QA output of the counter 11. b Indicates the QB output of the counter 11.

C Shows the QC output of the counter 11. This is an error detection signal indicating that four error pulses have been input. It is shown as the position (A) in the figure.

A Timing signal output from the timing generation counter 21 for one Sec cycle. b 10Se output from the timing generation counter 21
It is a timing signal of c cycles.

C This is a timing signal of 100 Sec cycle output from the timing generation counter 21. 1Sec generated by the timing generation counter 21,
It is a timing signal generated at 10 Sec and 100 Sec. In the figure, they are shown separately as (1), (10), and (100). Here, (A) shows that the error pulse "4" is detected, the timing generation counter 21 is also loaded with the timing signal of 10 Sec, and the counting is restarted from the initial state.

The output of the AND circuit 51 receives the error detection signal and the timing signal as inputs. Here, the error detection signal and the timing signal of 10 Sec
The output becomes "1" by the timing signal [shown as (10) in the figure].

This is the output of the OR circuit 71. This output is delayed by the delay circuit 72 to clear the counter 11, so that c and c are reset. This is an alarm signal output from the FF circuit 41. The output of counting and outputting four error pulses is output from the FF circuit 41 by using the signal of as a clock.

Timing signal of 1 Sec cycle, 10
The timing signal of the Sec cycle and the timing signal of the 100 Sec cycle are input to the AND circuits 61 to 63.
Since it is the AND circuit 61 that is set to (H), the timing signal of the 100 Sec cycle is the OR circuit 64.
Is output from.

In the time chart, one error pulse is input in (B), but no error pulse is input thereafter. Therefore, a, b, and c are stopped in a state of counting 1 and a timing signal of 100 Sec is input. At this point, the output of counting and outputting one error pulse is output from the FF circuit 41 and the counter 11 is reset.

FIG. 4 is a diagram for explaining another embodiment of the present invention. 4 shows a display circuit 81 provided in the embodiment of FIG. The display circuit 81 receives the output of the AND circuit 51 as an input and outputs a plurality of timing signals, for example, 1 Sec,
The error rate of the line is displayed on the display elements L1 to L3 by identifying which timing signal of 10 Sec or 100 Sec outputs the error detection signal.

For example, if the timing signal of 100 Sec is
Line error rate 10^-7If it corresponds to 10S
ec and 1Sec timing signals are line error rates
10 ^-610,^-FiveWill correspond to each error
The display elements L1 to L3 for displaying the rate are turned on.

[0034]

According to the present invention, even when the error occurrence status of a line having a low line error rate is monitored by a timing signal having a long cycle, when the line error rate deteriorates, it can be detected in a short time. Then, the alarm signal can be output, and the quality of the line can be maintained high by taking measures such as switching the line.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating the principle of the present invention.

FIG. 2 is a diagram illustrating an embodiment of the present invention.

FIG. 3 is a time chart of an example of the present invention.

FIG. 4 is a diagram for explaining another embodiment of the present invention.

FIG. 5 is a diagram illustrating a conventional example.

FIG. 6 is a time chart of a conventional example.

[Explanation of symbols]

1 Error Detection Circuit 10 Error Counting Means 11 Counter 20 Timing Generation Means 21, 22 Timing Generation Counter 30 Error Number Detection Means 31 NOR Circuit 40 Protecting Means 41 FF Circuit 50 Alarm Monitoring Means 51, 61-63
AND circuit 60 Selection means 64, 71 OR
Circuit 70 Logical sum means 72 Delay circuit 81 Display circuit L1 to L3 Display element

Claims (2)

[Claims] 1. An error detection circuit (1) for detecting a line error of a digital line, comprising: an error counting means (10) for counting an error pulse to be input; and the error counting means (10) for counting error pulses. Timing generating means (20) for generating a plurality of timing signals for performing an error, and an error for detecting that the count value of the error counting means (10) exceeds a first predetermined value and outputting an error detection signal. A number detection means (30); a protection means (40) which outputs a warning signal by detecting that the error detection signal output by the error number detection means (30) has continued a second predetermined value; At the time when the error detection signal of the error number detection means (30) is output, the closest timing among the plurality of timing signals generated by the timing generation means (20). Alarm monitoring means for taking a logical product of the ring signal (50), said timing generating means (20) a plurality of selecting means for selecting and outputting one of the timing signals generated in (60)
And an output from the alarm monitoring means (50) and an output from the selecting means (60), which is a logical sum means (70). The error number detecting means (30) detects the number of error pulses. The counting operation of the error counting means (10) is stopped by an error detection signal that is output upon detecting that the first predetermined value has been exceeded, and the error counting means (70) is output by the output of the logical sum means (70). An error detection circuit, which starts counting error pulses after resetting 10). 2. In the error detection circuit (1), the timing generation means (OR) is obtained by ORing the output of the alarm monitoring means (50) with the error detection signal output from the error number detection means (30). The error detection circuit according to claim 1, further comprising display means (80) for identifying a timing signal generated by (20) and displaying an error rate corresponding to the timing signal.