JP2606425B2 - Fault condition detection circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a fault state detection circuit, and more particularly to a circuit for detecting an AIS (Alarm Indication Signal) in digital transmission.

2. Description of the Related Art Conventionally, this type of fault state detection circuit includes an input "0" monitoring circuit 11 for detecting a value of "0" in input data 1 as shown in FIG. It is configured to include a counter 12 that counts up with an output, an AIS determination circuit 13, and a latch circuit 14 that latches the output of the determination circuit 13. Hereinafter, in the conventional fault state detection circuit, the AIS detection state is held when m pieces of "1" in the input data continue, and the number of "0" in the m pieces of input data is n in the AIS detection state. The operation will be described assuming that the AIS is canceled at the time above.

When the value of the input data 1 is “0”, the input “0” monitoring circuit 11 inputs information indicating that “0” is input to the counter 12. Thus, the counter 12 counts up.

Generally, if the input data 1 is a normal value, “0” and “1” are included at random. Therefore, if the value of “0” is n or more, a carry is output from the counter 12. As a result, the AIS determination circuit 13 determines that the state is the non-AIS state, and the determination result is held in the latch circuit 14.

If the carry from the counter 12 is not input, the AIS determination circuit 13 determines that the AIS state is established, and the determination result is held by the latch circuit 14. That is, when the count value of the counter 12 is less than n, the AIS state is held in the latch circuit 14 and notified to the outside. Note that n is a value smaller than m.

The above AIS detection operation is periodically performed by the control pulse 10 generated every m bits of the input data 1.
When the control pulse 10 is input, the counter 12 is reset and the count value becomes "0". Control pulse 10
Input, the AIS determination circuit 13 and the latch circuit 14
Set to IS state.

As described above, if n = 1, the output of the AIS determination circuit 13 transitions from the non-AIS state to the AIS state when there is no "0" in the m-bit data section where the control pulse 10 is generated, and the latch circuit It will be held at 14. As described above, the conventional failure state detection circuit detects an abnormal state in which "1" s are continuously detected by performing regular monitoring.

However, in the above-described conventional fault state detection circuit, since the monitoring section is determined by the control pulse,
There is a drawback that if m “1” s are continuous over the adjacent sections, it cannot be detected. That is, referring to FIG. 3, even if the m-bit data 32 over the monitoring sections 30 and 31 for the input data 1 is all “1”, it cannot be detected as the AIS state, and the effective fault state cannot be detected. There was a drawback that it should not be.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional disadvantages, and an object of the present invention is to provide a fault state detection circuit capable of more effectively detecting a fault state.

The fault state detecting circuit according to the present invention comprises a first detecting means for detecting that the value of digital data inputted is a specific number of m consecutive values, and a response to the detection of the specific number of m digital values. Means for outputting a message indicating that a fault is detected, and m of the value of the digital data input in the fault detected state.
A second detecting means for detecting that n (n <m) of the specified values are inverted values of the specific value; and a means for canceling the fault in response to the detection of the n inverted values. It is characterized by the following.

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of a fault condition detection circuit according to the present invention. In the figure, a fault state detection circuit according to an embodiment of the present invention includes an m-bit shift register 6 and an input “0” monitoring circuit 5 for monitoring “0” of input data 1 to the m-bit shift register 6. , The output “0” monitoring circuit 7 for monitoring “0” of the data output from the m-bit shift register 6 and counting up when the input “0” monitoring circuit 5 detects “0”, and the output “0” When the monitoring circuit 7 detects “0”, an up / down counter 8 that counts down and an input “1” that monitors input data “1”.
The monitoring circuit 2 and the input "1" are counted up when the monitoring circuit 2 detects "1". If not, the counter 3 is reset to "0". When the value of the up / down counter 8 becomes n,
And an AIS determination circuit 4 for detecting an AIS state. The up / down counter 8 performs a counting operation in a range from “0” to “m”, and outputs a carry when the count value reaches “n”. When the count value reaches "m", the counter 3 outputs a carry.

The AIS determination circuit 4 is composed of a well-known RS flip-flop. The carry of the counter 3 is input to its set terminal, and the carry of the up / down counter 8 is input to its reset terminal.

Therefore, the AIS determination circuit 4 determines that the value of the counter 3 is m
When the value of the up / down counter 8 is n, the non-AIS state is output.

The m-bit shift register 6 is formed by cascade connection of well-known D-type flip-flops at m stages, and performs a shift operation by a clock synchronized with the input data 1. The initial value of the m-bit shift register 6 is all "0".

In such a configuration, when the input data 1 is “1”,
A pulse is output from the input “1” monitoring circuit 2 and the counter 3
Is counted up. When the input data 1 is “0”, the counter 3 is reset by the output of the input “0” monitoring circuit 5. Therefore, the carry is output from the counter 3 only when the input data 1 is m consecutive “1” s, and the AIS determination circuit 4 is set to the AIS state.

This enables real-time monitoring, unlike the conventional method of performing regular monitoring.

By the way, once an abnormal state in which "1" of the input data 1 continues occurs once, the state continues to be held by the AIS determination circuit 4, but may be recovered later. It is the input "0" monitoring circuit 5, the m-bit shift register 6, the output "0" monitoring circuit 7, and the up / down counter 8 that determine whether or not the recovery state is established.

When the input data 1 is "0", a pulse is output from the input "0" monitoring circuit 5, and the up / down counter 8 counts up. At this time, if “0” is output from the m-bit shift register 6, the up / down counter 8 is counted down by a pulse output from the output “0” monitoring circuit 7. Therefore, the up / down counter 8 always indicates the number of “0” in the m-bit shift register 6.

By the way, if the above input data 1 is m consecutive “1” s, a carry is output from the counter 3 and
The up / down counter 8 does not count up at all,
The counter value continues to be counted down and becomes “0”. After the count value is "0", if the count value of the up / down counter 8 becomes "n" in m successive bits, that is, the input data 1 starts to show "0" and reaches n. In this case, it is considered that the system has recovered from the failure.
In such a case, a carry is output from the up / down counter 8, and the AIS determination circuit 4 is reset to output a non-AIS state.

In the above operation, if the values of m and n are appropriately determined according to the type of the input data, the transmission speed, and the like, the fault state monitoring can be performed more effectively. For example, DI of each counter
A P-type switch may be provided so that the values of m and n can be set from outside.

Note that when m pieces of input data are continuously “0”, a failure can be detected. In this case, the operation is an operation in which “1” and “0” are exchanged in the above description of the operation.

Effect of the Invention As described above, the present invention constantly monitors the state of continuous m specific values of input data and sets a failure state,
If there are n inversions of the specific value in the subsequent m bits, the failure state is set, so that the failure state can be more effectively detected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a fault state detection circuit according to an embodiment of the present invention, FIG. 2 is a block diagram showing a configuration of a conventional fault state detection circuit, and FIG. 3 shows a conventional fault state detection method. It is a conceptual diagram. Explanation of Signs of Main Parts 2 ... Input "1" Monitoring Circuit 3 ... Counter 4 ... AIS Judgment Circuit 5 ... Input "0" Monitoring Circuit 6 ... m-bit Shift Register 7 ... Output "0" Monitoring Circuit 8 Up-down counter

Claims (1)

(57) [Claims] A first detecting means for detecting that a value of digital data to be inputted is a specific value of m successively;
Means for outputting a fault detection state in response to the detection of the m specific values; and n (n <m) of the m digital data values input in the fault detection state, A fault state detection circuit comprising: a second detection unit for detecting an inverted value of a specific value; and a unit for canceling a fault in response to detection of the n inverted values.