JPH0728748Y2 - Alarm display signal detection method - Google Patents

Description

[Detailed Description of the Invention] [Industrial field of application] The present invention relates to an alarm indication signal (AIS).
l) Detection method, especially AIS detection method for digital transmission communication.

[Conventional technology]

The AIS detection method from the intermediate relay device in digital transmission communication is that the reception side of the terminal relay device monitors the received signal from the synchronized intermediate relay device for each 6-bit code and
A comparator is used that compares the voltage of the AIS received signal that becomes a high level output for one bit when the S code (101010) is detected with the threshold value that holds a constant voltage.

An example of such an AIS detection method is shown in FIG. The comparator 41 shown in FIG. 4 inputs the above-mentioned AIS reception signal and the threshold value, and if the threshold voltage is lower, displays "intermediate repeater AIS issue" fault display. On the contrary,
If the threshold voltage is higher than the voltage of the AIS reception signal, the operation to clear the fault display is performed.

[Problems to be solved by the device]

In this conventional AIS detection method from the intermediate relay device, analog processing is performed using a comparator. For this reason,
When the circuit is constructed, the number of parts increases, digital processing such as LSI processing cannot be performed, and the mounting area also increases.

In addition, the threshold value of the input of the comparator fluctuates due to the characteristics of each element due to the change of the environment, especially the temperature, and the characteristic of the comparator body also changes due to the temperature change. , It is no longer possible to represent the probability of being undetectable.

Further, due to variations (errors) in the manufacturing lots of the respective elements, even in the same apparatus using the same elements, there are various problems such as individual differences when strictly compared.

An object of the present invention is to provide an AIS detection method in which the circuit configuration is digitized in order to eliminate such a defect.

[Means for Solving the Problems]

In order to achieve the above object, the present invention connects a terminal of a D flip-flop to one input terminal of one OR gate, and connects an output terminal of the OR gate to a first reset type D flip-flop and a second reset type. Connected to the C terminals of the D flip-flop, the third reset type D flip-flop, and the fourth reset type D flip-flop, and connecting the Q terminal of the first reset type D flip-flop to the D terminal of the second reset type D flip-flop. Then, the Q terminal of the second reset type D flip-flop is connected to the D of the third reset type D flip-flop.
Q of the third reset type D flip-flop connected to the terminal
A terminal is connected to the D terminal of the fourth reset D flip-flop, a Q terminal of the fourth reset D flip-flop is connected to the D terminal of the first set reset D flip-flop, and a first set reset D flip-flop is connected. Is connected to the D terminal of the second set-reset type D flip-flop and the first input terminal of one 4-input AND gate,
The terminal of the set-reset D flip-flop is connected to the first input terminal of the other 4-input AND gate, and the Q terminal of the second set-reset D flip-flop is connected to the D terminal of the third set-reset D flip-flop and one of 4-input AN
It is connected to the second input terminal of the D gate, the terminal of the second set-reset D flip-flop is connected to the second input terminal of the other 4-input AND gate, and the Q terminal of the third set-reset D flip-flop is connected to the second terminal. Connected to the D terminal of the 4-set reset type D flip-flop and the third input terminal of one 4-input AND gate, and connecting the terminal of the third set-reset type D flip-flop to the third input terminal of the other 4-input AND gate Then, the Q terminal of the fourth set-reset D flip-flop is connected to the fourth input terminal of the one 4-input AND gate, and the terminal of the fourth set-reset D flip-flop is the fourth input of the other 4-input AND gate. Connected to one end, the output end of one 4-input AND gate is connected to the S terminal of the flip-flop, the output end of the other 4-input AND gate is connected to one input end of the other OR gate, and the other OR Game The output terminal of is connected to the R terminal of the flip-flop, the alarm display reception signal is input to the D terminal of the D flip-flop, and the clock pulse is input to the C terminal of the D flip-flop and the other input terminal of one OR gate. A reset pulse is input to the R terminals of the first reset D flip-flop, the second reset D flip-flop, the third reset D flip-flop, and the fourth reset D flip-flop;
A multi-frame cycle clock pulse is input to the C terminals of the set-reset D flip-flop, the second set-reset D flip-flop, the third set-reset D flip-flop, and the fourth set-reset D flip-flop, R terminal of one set reset type D flip-flop, second set reset type D flip-flop, third set reset type D flip-flop, and fourth set reset type D flip-flop, and OR of the other
A reset pulse is input to the other input terminal of the gate when the power is turned on, and a failure occurrence display signal is output from the Q terminal of the flip-flop.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.
The AIS detection method shown in FIG. 1 is composed of an AIS detection unit 10 and a protection circuit unit 20.

The AIS detection unit 10 of such an AIS detection system monitors the received signal on the receiving side of the digital transmission device, and when the AIS code, for example, (101010) is detected, the AIS received signal which becomes a high level output for one bit. And a timing signal whose output pulse is a clock 5 times in one multi-frame and a 1-bit reset pulse in one multi-frame. Then, the AIS detection unit 10 monitors the AIS received signal several times at a fixed position in one multiframe, and when the AIS received signal is detected more than a specified number of times in one multiframe, the AIS received signal is detected.
Send a detection signal.

An example of such an AIS detector is shown in FIG.
As shown in FIG. 2, this AIS detection section includes a D flip-flop 11, an OR gate 12, and reset type D flip-flops 13 to 16.

In the D flip-flop 11, the AIS reception signal is AIS with the clock pulse selected five times in one multiframe.
Whether or not it is in the reception state (high level input) (low level input) is determined. In the OR gate 12, the clock pulse is sent to the reset type D flip-flops 13 to 16 only when the determination result of the D flip-flop 11 is the AIS receiving state (when the output of the D flip-flop 11 is low level). The D input of the reset D flip-flop 13 is fixed to the high level. As a result, the reset-type D flip-flops 13 to 16 have 4 cycles within the reset pulse cycle output once in one multiframe.
When a clock pulse is sent from the OR gate 12 more than once, it operates to output an AIS detection signal (the output at the time of detection is high level).

The protection circuit unit 20 receives an AIS detection signal as a timing signal and a reset signal. Then, when the AIS detection signal from the AIS detection unit 10 is continuously transmitted for several multiframes, AIS detection is performed. On the contrary, when the AIS detection signal from the AIS detection unit 10 is not transmitted for several consecutive frames, the AIS detection is canceled.

An example of such a protection circuit section 20 is shown in FIG. As shown in FIG. 3, this protection circuit includes set / reset D flip-flops 21 to 24, 4-input AND gates 25 and 26, a flip-flop 27, and an OR gate 28.

Next, the operation of this embodiment will be described.

First, the AIS detection unit 10 latches an AIS reception signal by using a pulse transmitted five times in one multiframe as a clock. Then, when the AIS reception signal is latched at a high level indicative of AIS code reception four times or more among the clocks transmitted five times in one multiframe, it is transmitted to the protection circuit unit 20 as an AIS detection signal (high level). Also, by using a reset pulse output at a fixed position of 1 bit in one multi-frame, the four-stage shift register including the reset type D flip-flops 13 to 16 is always reset once in one multi-frame.

On the other hand, the initial reset pulse applied to the protection circuit section 20 is a power-on reset pulse for bringing the output into a normal state when the power is turned on. The protection circuit unit 20 latches the AIS detection signal sent from the AIS detection unit 10 with a clock pulse of one multiframe period. Then, the protection circuit unit 20 sets the set-reset flip-flops 21 to 24 when the AIS detection signal is at the high level four times in a row (4 multiframes) in succession, and the "intermediate relay device AIS issuance" is externally set. Display a fault. On the contrary, when the AIS detection signal is at the low level for four consecutive multi-frames, the protection circuit section 20 causes the set-reset flip-flops 21-24.
To reset the fault display.

The set-reset flip-flop holds the state in the above-mentioned intermediate state.

As described above, in this embodiment, the reception side of the digital transmission device monitors the received signal and the AIS code (for example, 101010) is received.
AIS received signal that becomes high level output for 1 bit when it is detected and AIS received signal is monitored several times at a fixed position in one multi-frame, and the specified number of times is exceeded in one multi-frame.
AIS that sends AIS detection signal when AIS received signal is detected
AIS detection is performed when the AIS detection method is continuously transmitted for several multi-frames, and conversely, when the AIS detection signal is not transmitted for several multi-frames continuously.
And a protection circuit section for canceling the detection.

[Effect of device]

As described above, the present invention can be entirely digitized by including the detection unit and the protection circuit unit.
It becomes possible to convert to I. The number of parts is reduced, the mounting area is reduced, and even if the environment such as temperature changes, LS
Since I is made into one chip, variations are eliminated, and individual differences do not occur even if manufacturing lots are different. Further, since all can be digitized, there is an effect that the probability of false detection and the probability of non-detection can be quantitatively expressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the AIS detection unit of FIG. 1, and FIG. 3 is an example of the protection circuit unit of FIG. The circuit diagram shown in FIG. 4 is a block diagram showing a constant state of the conventional AIS detection method. 10 …… AIS detector 21 …… Protection circuit

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Creator Makoto Mizuno 1-4-2 Mita, Minato-ku, Tokyo Mita International Building, NEC Transmission Engineering Co., Ltd. (56) Reference JP-A-1-316040 (JP, A) Japanese Patent Laid-Open No. 63-90236 (JP, A) Actually developed 62-71927 (JP, U)

Claims (1)

[Scope of utility model registration request] 1. A terminal of a D flip-flop is connected to one input end of one OR gate, and an output end of the OR gate is connected to a first reset type D flip-flop, a second reset type D flip-flop, and a third reset. Formula D flip-flop,
And connecting the C terminal of the fourth reset D flip-flop, the Q terminal of the first reset D flip-flop to the D terminal of the second reset D flip-flop, and the Q of the second reset D flip-flop. The terminal is connected to the D terminal of the third reset D flip-flop, the Q terminal of the third reset D flip-flop is connected to the D terminal of the fourth reset D flip-flop, and the Q of the fourth reset D flip-flop is connected. The terminal is connected to the D terminal of the first set-reset D flip-flop, and the Q terminal of the first set-reset D flip-flop is connected to the second set-reset D
Connect the D terminal of the flip-flop and the first input terminal of one 4-input AND gate, and connect the terminal of the first set-reset D flip-flop to the first input terminal of the other 4-input AND gate to set the second set. The Q terminal of the reset type D flip-flop is connected to the D terminal of the third set reset type D flip-flop and the second input terminal of one 4-input AND gate, and the terminal of the second set reset type D flip-flop is connected to the other 4 side. It is connected to the second input terminal of the input AND gate and the Q terminal of the third set-reset type D flip-flop is connected to the fourth terminal.
Connected to the D terminal of the set-reset D flip-flop and the third input terminal of one 4-input AND gate, and the terminal of the third set-reset D flip-flop to the other 4 inputs
It is connected to the third input terminal of the AND gate, the Q terminal of the fourth set-reset D flip-flop is connected to the fourth input terminal of one 4-input AND gate, and the terminal of the fourth set-reset D flip-flop is the other. 4th AND gate of 4th
Connected to the input end, the output end of one 4-input AND gate is connected to the S terminal of the flip-flop, the output end of the other 4-input AND gate is connected to one input end of the other OR gate, and the other The output end of the OR gate is connected to the R terminal of the flip-flop, the alarm display reception signal is input to the D terminal of the D flip-flop, and the clock pulse is input to the C terminal of the D flip-flop and the other input end of one OR gate. Input,
First reset type D flip-flop, second reset type D
A reset pulse is input to the R terminals of the flip-flop, the third reset D flip-flop, and the fourth reset D flip-flop, and the first set reset D flip-flop, the second set reset D flip-flop, and the third set reset D flip-flop A 1-multiframe cycle clock pulse is input to the C terminals of the set-reset D flip-flop and the fourth set-reset D flip-flop,
Power supply to the R terminal of the set-reset D flip-flop, the second set-reset D flip-flop, the third set-reset D flip-flop, and the fourth set-reset D flip-flop, and the other input terminal of the other OR gate An alarm display signal detection method characterized in that a reset pulse is input at the time of application and a failure occurrence display signal is output from the Q terminal of the flip-flop.