JP3469710B2 - Clock monitoring device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock monitoring device, and more particularly to a device for monitoring stop (interruption) of clock supply. In a digital sequential circuit, when the supply of the clock is stopped, the operation of the circuit is stopped. Therefore, it is usual to detect the disconnection of the clock and secure the clock supply source in an emergency. In general, a plurality of clock sources are provided, a plurality of paths are provided from one clock source, and supply is performed to a target digital sequential circuit.

The supply side selects any one of the plurality of clock supplies, but its operation is usually selected based on the disconnection alarm of the clock disconnection monitoring circuit. In such a case, the detection of the disconnection alarm of the clock disconnection monitoring circuit does not necessarily mean that the disconnection is detected immediately, but it means that the clock source to be selected is changed. Therefore, some protection is required.

Generally, a monostable multivibrator or the like is used to disconnect when there is no clock edge for a certain period of time, or the clock disconnection monitoring circuit itself has an internal oscillator for monitoring, which allows a certain period of time. There is a method of issuing an alarm depending on the presence or absence of a clock edge.

[0004]

2. Description of the Related Art FIG. 21 is a block diagram showing an example of a conventional clock loss monitoring device. In FIG.
A clock to be monitored as shown in (A) comes in and is supplied to the disconnection detector 12. A counting clock as shown in FIG. 22B is input to the terminal 11 and supplied to the counter 14. The disconnection detection unit 12 is composed of, for example, a monostable multivibrator (monomulti), and has a cycle T of the clock to be monitored.
has a time constant larger than α, for example, 1.5 × Tα,
Within the period T ₁ of the counting clock, if the monitored clock rises within this period 2 · Tα, a low level disconnection detection signal is generated at the low level, and if the monitored clock does not rise, a high level disconnection detection signal is generated, and the counter 14 is generated. Supply. The counter 14 is for setting the protection time T _P. For example, when the protection time T _P is the same as the counting clock cycle T ₁ ,
As shown in FIG. 22C, when the high level disconnection detection signal is supplied within the period T ₁ , a high level disconnection alarm signal is output, and if the high level disconnection detection signal is not supplied within the period T ₁ . Output low level. The high level disconnection alarm signal is latched by the latch section 16 and output from the terminal 17.

[0005]

In the conventional device, the time T ₂ from when the clock to be monitored is cut off until the disconnection alarm is issued is within the protection time T _P (in this case T _P = T ₁ ). Fluctuates with. For example, FIG. 23 if the rise of the counting clocks shown in (B) is early with respect to the rising edge of the last pulse of the monitoring target clock as shown in (A) substantially time from clock loss as shown in FIG. (C) T ₁ A disconnection alarm will be issued later,
If the rising edge of the counting clock is late with respect to the rising edge of the last pulse of the monitored clock, the disconnection alarm will be issued approximately 2 × T ₁ after the clock disconnection, as shown in FIG.

Slow data in new synchronous (SDH) systems
ITU international at each speed level when demultiplexing signals
Overhead data processing specified in the recommendation is performed.
Multiple low speed signals into one high speed signal and vice versa
In the process of separation into
It Therefore, as shown in FIG. 24, the processing circuit 20₁, 2
0₂, ... 20_nThe black selected by the selector 22 is assigned to each.
Clock divider or multiplier circuit 21 ₁, 21₂,… 21_nRespectively
Synchronized clocks that are divided or multiplied by
To be done.

In each of the processing circuits 20 _{1 to} 20 _n described above, a disconnection alarm is issued when a disconnection of the clock separated from the input data occurs, but if a clock disconnection occurs in the processing circuit 20 ₁ on the upstream side, subsequent processing is performed. circuit 20 _2, the clock loss ... 20 _n, even late in the order. In this case, if there is a large variation in protection time in the clock monitoring device provided in each processing circuit,
The processing circuit 20 ₂ issues the clock loss alarm before the processing device 20 ₁ on the upstream side, and the location of the failure cannot be specified.

[0008] Such a variation in protection time is reduced.
To count, the counting clock cycle T ₁To make that smaller
Count value that the counter 14 outputs at high level for the minutes
Must be increased. However, the counter 14
To increase the count value, the counter
The number of lip flops has increased, and the circuit scale of the entire device has increased.
There was a problem of increasing the size.

The present invention has been made in view of the above points,
An object of the present invention is to provide a clock monitoring device in which variations in protection time are small, the number of flip-flops forming a counter is small, and the circuit scale can be reduced.

[0010]

According to a first aspect of the present invention, an error is detected after a detection unit for detecting at least one of disconnection and recovery of a clock to be monitored and a detection signal of the detection unit is supplied. A delay circuit that outputs a delay signal after a predetermined time including: a counter that supplies the detection signal and then counts a counting clock to generate a mask signal having a time width larger than the error of the delay circuit; And a decoder for removing the error of the delay signal from the signal and outputting as a detection signal provided with a protection time.

Therefore, even if the cycle of the counting clock is shortened, the counter only needs to generate a mask signal having a time width larger than the error of the delay circuit, so that the number of flip-flop stages can be reduced and the circuit scale can be reduced. In addition, it is possible to obtain a detection signal with high accuracy and small variation in protection time.

According to a second aspect of the present invention, in the clock monitoring device according to the first aspect, the delay circuits and the decoders are cascade-connected. This makes it possible to set a long delay time, which is impossible with a single delay circuit, that is, a protection time, and to obtain a detection signal with a small variation in the protection time.

According to a third aspect of the present invention, in the clock monitoring apparatus according to the first aspect, the delay circuit and the counter are selected by switching between the disconnection detection signal and the disconnection recovery detection signal output from the detection section. It has a first selector for supplying, and makes the protection times of the disconnection detection and the disconnection recovery detection the same.

As a result, the delay circuit, the counter, and the decoder can be shared by the disconnection detection and the disconnection recovery detection, and the circuit scale can be further reduced. The invention according to claim 4 is the invention according to claim 2.
In the clock monitoring device described above, there is provided a first selector which selectively selects the disconnection detection signal and the disconnection recovery detection signal output by the detection unit and supplies the detection signal to the delay circuit and the counter. The protection time for each detection is the same.

As a result, the disconnection detection and the disconnection recovery detection can share the delay circuit and the decoder connected in cascade with the counter, and the circuit scale can be further reduced. According to a fifth aspect of the present invention, in the clock monitoring apparatus according to the fourth aspect, the output signals of different decoders in the cascade-connected decoders are selectively selected and output as detection signals at the time of disconnection detection and at the time of disconnection recovery detection. It has a second selector.

For this reason, the protection times for the disconnection detection and the disconnection recovery detection can be greatly different, and a part of the circuit can be shared to reduce the circuit scale. According to a sixth aspect of the present invention, in the clock monitoring device according to the first or fifth aspect, the delay circuit and the counter are switched by selecting the disconnection detection signal and the disconnection recovery detection signal output from the detection unit. The counter has a first selector for supplying, and the counter generates a mask signal having a different time width at the time of detection of disconnection and at the time of detection of recovery from disconnection.

For this reason, the protection times for the disconnection detection and the disconnection recovery detection can be differentiated with high accuracy, and a part of the circuit can be shared to reduce the circuit scale.

[0018]

1 shows a block diagram of a first embodiment for detecting a clock loss according to the present invention. In the figure, terminal 30
2A, a counting clock as shown in FIG. 2A comes in and is supplied to the counter 32. The clock to be monitored enters the terminal 31 and is supplied to the disconnection detector 34. The disconnection detection unit (detection unit) 34 has a time constant larger than the period Tα of the clock to be monitored, for example, 1.5 × Tα.
When there is no rise of the clock to be monitored within the period, a disconnection detection signal as shown in FIG. 2 (C) which is high level is generated and supplied to the counter 32 and the monomulti 36.

The mono-multi (delay circuit) 36 is for setting a protection time T _P1 for detecting a clock break. When a high-level break detection signal is supplied, the mono-multi (delay circuit) 36 substantially passes the protection time T _P1 , A rising signal as shown in FIG. 2D is generated and supplied to the decoder 38. However, the protection time T _P1 measured by the mono-multi 36 has a variation error T ₂ (however, T ₂ << T _P1 ) due to an error in capacitance and resistance and a temperature variation.
The counter 32 divides the frequency by counting the counting clock, generates a mask signal as shown in FIG. 2B in which the half cycle T ₃ is larger than twice the fluctuation error T ₂ , and the decoder 3
Supply to 8.

In this case, the decoder 38 is constituted by an AND circuit, and when the output of the counter 32 is at high level, the output of the monomulti 36 is taken out and supplied to the latch section 40. The latch unit 40 latches the high level disconnection alarm signal output from the decoder 38 and outputs it from the terminal 41 as shown in FIG.

As described above, the monomulti 36 measures the protection time T _P with a simple circuit structure, but has a fluctuation error T ₂ . The counter 32 divides the count clock to generate a half cycle of T
_Since a signal of ₃ (> 2 × T ₂ ) is obtained, the frequency division ratio in the counter 32 is small and the number of stages of flip-flops forming the counter 32 is small. By calculating the output of the mono-multi 36 with the output of the counter 32, the protection time T for disconnection detection is calculated.
_{It is possible} to accurately specify _P, and it is possible to reduce the number of flip-flops forming the counter 32 and simplify the circuit configuration.

FIG. 3 shows a second example of the clock loss detection of the present invention.
3 shows a block diagram of an embodiment. In FIG.
The counter 32 receives the counting clock as shown in FIG.
Is supplied to. The clock to be monitored enters the terminal 31 and is supplied to the disconnection detector 34. The disconnection detector 34 has a time constant larger than the period Tα of the monitored clock, for example, 1.5 × Tα, and becomes high level when the monitored clock does not rise within this 1.5 × Tα period. ),
A disconnection detection signal as shown in (F) is generated and supplied to the counter 32 and the monomulti 36.

The mono-multi (delay circuit) 36 is for setting the protection time T _P1 for detecting a clock break, and when a high-level break detection signal is supplied, after a substantial protection time T _P1 elapses, A rising signal shown in FIG. 4D is generated and supplied to the decoder 38. However, the protection time T _P1 measured by the mono-multi 36 has a variation error T ₂ (however, T ₂ << T _P1 ) due to an error in capacitance and resistance and a temperature variation.
The counter 32 divides the frequency by counting the counting clock, generates a mask signal as shown in FIG. 4B in which the half cycle T ₃ is larger than twice the fluctuation error T ₂ , and the decoder 3
Supply to 8,44,50 respectively.

In this case, the decoder 38 is composed of an AND circuit, and when the output of the counter 32 is at high level, the output of the monomulti 36 is taken out and supplied to the latch section 40. The latch unit 40 latches the high level disconnection alarm signal output from the decoder 38 and supplies it to the monomulti 42 as shown in FIG.

The mono-multi 42 is for setting the protection time T _P2 , and when the output of the latch unit 40 at the high level is supplied, it rises after the substantial protection time T _P2 has passed.
The signal shown in (G) is generated and supplied to the decoder 44.
However, the protection time T _P2 has a variation error T ₂ (<< T _P2 ). The decoder 44 is the counter 32 shown in FIG.
When the output is high level, the output of mono-multi 42 is shown in Fig. 4.
As shown in (H), it is latched by the take-out latch section 46 and supplied to the subsequent mono-multi.

The n-th mono-multi 48 is for setting the protection time T _Pn , and when the output of the latch unit at the high stage of the high level is supplied, a signal which rises after the substantial protection time T _Pn has elapsed. Is generated and supplied to the decoder 50. However,
The protection time T _Pn has a variation error T ₂ (<< T _P2 ).
When the output of the counter 32 shown in FIG. 4 (F) is at a high level, the decoder 50 latches the output of the monomulti 48 by the take-out latch section 52 and outputs it from the terminal 54 as shown in FIG. 4 (H).

In this way, the protection time (T _P1 +
T _P2 + ... T _Pn ) can be extended, and in this case also, the protection time for disconnection detection can be set to an accurate value. FIG. 5 shows the third aspect of the present invention.
3 shows a block diagram of an embodiment. In the figure, the clock loss detection is performed in FIG. 1, whereas the clock loss recovery detection is performed in the present embodiment. A counting clock as shown in FIG. 6A enters the terminal 60 and is supplied to the counter 62. The clock to be monitored enters the terminal 61 and is supplied to the disconnection detector 64. The disconnection detector 64 has a time constant of, for example, 1.5 × Tα, which is larger than the period Tα of the monitored clock.
When there is no rise of the clock to be monitored within the period of 1.5 × Tα, a disconnection detection signal which becomes high level is generated, and this disconnection detection signal is inverted by the inverter 65 to be a signal as shown in FIG. And the monomulti 66. In this embodiment, the disconnection detector 64 and the inverter 65 constitute a detector.

The mono-multi 66 is for setting the protection time T _P1 for detecting the clock loss, and is a diagram which rises after the substantial protection time T _P1 has elapsed when the high level inversion detection signal is supplied. 6 (D) is generated and supplied to the decoder 68. However, the protection time T _P1 measured by the monomulti 66 has a variation error T ₂ (however, T ₂ << T _P1 ) due to an error in capacitance and resistance and a temperature change. The counter 62 divides the frequency by counting the counting clock, and the half cycle T ₃ is larger than twice the fluctuation error T ₂ .
A mask signal as shown in (B) is generated and supplied to the decoder 68.

In this case, the decoder 68 is composed of an AND circuit, and when the output of the counter 62 is at the high level, the output of the monomulti 66 is taken out and supplied to the latch section 70. The latch unit 70 latches the high level disconnection alarm signal output from the decoder 68 and outputs it from the terminal 71 as shown in FIG.

As described above, the monomulti 66 measures the protection time T _P with a simple circuit structure, but has a fluctuation error T ₂ . The counter 62 divides the count clock and divides the half cycle by T.
A signal of ₃ (> 2 × T ₂ ) is obtained, and the frequency division ratio of the counter 62 is small, and the number of flip-flops forming the counter 62 is small. By calculating the output of the mono-multi 66 with the output of the counter 62, the protection time T for recovery from disconnection is calculated.
_P can be accurately defined, and the number of flip-flops forming the counter 62 can be reduced to simplify the circuit configuration.

FIG. 7 shows a block diagram of a fourth embodiment for detecting recovery from clock loss according to the present invention. In the figure, a counting clock is input to the terminal 60 and supplied to the counter 62.
The clock to be monitored enters the terminal 61 and is supplied to the disconnection detector 64. The disconnection detector 64 determines the period T of the monitored clock.
has a time constant larger than α, for example, 1.5 × Tα,
When there is no rise of the clock to be monitored within this 1.5 × Tα period, a disconnection detection signal which becomes high level is generated, and this disconnection detection signal is inverted by the inverter 65 and supplied to the counter 62 and the monomulti 66.

Mono-multi 66 protects against clock loss detection
Interval T_P1This is for setting the
When the detection signal is supplied, the approximate protection time T_P1Has passed
After that, a rising signal is generated and supplied to the decoder 68. Was
However, the protection time T measured by the Mono Multi 66_P1Is the capacity
And fluctuation error T due to resistance error and temperature fluctuation₂(However, T
₂≪T_P1)have. The counter 62 is a counting clock.
The frequency is divided by counting₃Fluctuates
Error 2 × T₂Generate larger mask signal and decoder
Supply to 68, 74 and 80 respectively.

In this case, the decoder 68 is composed of an AND circuit, and when the output of the counter 62 is at the high level, the output of the monomulti 66 is taken out and supplied to the latch section 70. The latch unit 70 latches the high level disconnection alarm signal output from the decoder 68 and supplies it to the monomulti 72.

The mono-multi 72 is for setting the protection time T _{P2. When} the output of the latch unit 70 at the high level is supplied, the mono-multi 72 generates a signal which rises after the substantial protection time T _P2 has passed. It is supplied to the decoder 74. However, protection time T
_P2 has a variation error T ₂ (<< T _P2 ). Decoder 7
4 is monomulti 7 when the output of the counter 62 is high level
The two outputs are taken out and latched by the latch unit 76 and supplied to the subsequent mono-multi.

The n-th _{monomulti circuit} 78 is for setting the protection time T _Pn , and when the output of the latch unit of the preceding stage of high level is supplied, it is a signal which rises after the substantial protection time T _Pn has elapsed. Is generated and supplied to the decoder 80. However,
The protection time T _Pn has a variation error T ₂ (<< T _P2 ).
When the output of the counter 62 shown in FIG. 4 (F) is at high level, the decoder 80 takes out the output of the monomulti 78 by the latch section 82 and outputs it from the terminal 84.

In this way, the protection time for recovery from disconnection can be extended by connecting the multi-multi, the decoder and the latch section in cascade, and in this case as well, the protection time for recovery from disconnection (T _P1 + T _P2 + ...
T _Pn ) can be an accurate value. By the way, in the case of detecting the clock loss recovery, as a modification of the circuit shown in FIG. 5, the monitoring target clock may be supplied to the counter 62 as the counting clock as shown in FIG. In this case, when the monitored clock shown in FIG. 9A is recovered and there is a pulse loss as shown by the broken line, recovery of the clock interruption is delayed and the interruption alarm is as shown in FIG. 9B.

Since it is desirable to count the protection time for disconnection recovery after a normal clock having no loss is input, the counter 62 may be reset by the disconnection detection signal. FIG. 10 is a block diagram of a fifth embodiment of the present invention, which detects clock interruption and interruption recovery in the same protection time. In the figure, a counting clock is input to the terminal 60 and supplied to the counter 88. The clock to be monitored enters the terminal 61 and is supplied to the disconnection detector 64. Disconnection detector 6
Reference numeral 4 denotes a period which is larger than the period Tα of the monitored clock, for example, a time constant of 1.5 × Tα, and becomes high level when the monitored clock does not rise within this 1.5 × Tα period. Such a disconnection detection signal S1 is generated and supplied to the inverter 65 and the selector 90. The inverter 65 inverts the disconnection detection signal S1 and supplies the inverted disconnection detection signal S2 shown in FIG. 11B to the first selector 90. The selector 90 outputs the signal S1 or S depending on the output of the latch unit 92.
2 is selected, a selection signal shown in FIG. 11C is generated and supplied to the counter 88 and the monomulti 66.

The mono-multi 66 is for setting the protection time T _P1 for detecting the clock loss, and when a high-level selection signal is supplied, the mono-multi 66 rises after the substantial protection time T _P1 has elapsed. The decoder 68 generates a signal as shown in E).
Supply to. However, the protection time T _P1 measured by the monomulti 66 has a variation error T ₂ (however, T ₂ << T _P1 ) due to an error in capacitance and resistance and a temperature change. Counter 88
Divides by counting the counting clock when the selection signal is at the high level, and generates the MSK pulse as shown in FIG. 11D in which the half cycle T ₃ is larger than twice the fluctuation error T ₂ and the selection signal Goes low, an INH pulse is generated and supplied to the decoder 68.

In this case, the decoder 68 is composed of an AND circuit, and when the output of the counter 62 is at a high level, the output of the monomulti 66 is taken out and the signal shown in FIG. The flip-flop 92 is a T-type flip-flop whose output level is inverted at the rising edge of the signal output from the decoder 68. The flip-flop 92 generates the disconnection alarm signal shown in FIG. . This disconnection alarm signal indicates a disconnection of the clock at a high level.

As described above, the monomulti 66 measures the protection time T _P with a simple circuit structure, but has a fluctuation error T ₂ . The counter 88 divides the count clock to generate a half cycle of T
_{Since 3} (> 2 × T ₂ ) MSK pulses and INH pulses are obtained, the frequency division ratio of the counter 88 is small and the number of flip-flop stages forming the counter 88 is small. By calculating the output of the mono-multi 66 with the output of the counter 88, the protection time T _P for the disconnection detection and recovery can be accurately defined, and the number of flip-flops forming the counter 88 can be reduced to simplify the circuit configuration.

FIG. 12 shows a block diagram of a sixth embodiment of the present invention, which detects a clock break and a break recovery in the same protection time. In the figure, a counting clock is input to the terminal 60 and supplied to the counter 62. The clock to be monitored enters the terminal 61 and is supplied to the disconnection detector 64. The disconnection detection unit 64 has a period larger than the period Tα of the monitored clock, for example, 1.5
It has a time constant of × Tα, and becomes high level when the monitored clock does not rise within this 1.5 × Tα period.
3 (A), the disconnection detection signal S1 is generated and supplied to the inverter 65 and the selector 90. The inverter 65 inverts the disconnection detection signal S1 and supplies the inverted disconnection detection signal S2 shown in FIG. The selector 90 selects the signal S1 or S2 by the output of the latch unit 92,
The selection signal shown in FIG. 13M is generated and supplied to the counter 62 and the monomulti 66.

The mono-multi 66 is for setting the protection time T _P1 for detecting the clock loss, and when a high-level selection signal is supplied, the mono-multi 66 rises after the substantial protection time T _P1 has elapsed. The decoder 68 generates a signal as shown in E).
Supply to. However, the protection time T _P1 measured by the monomulti 66 has a variation error T ₂ (however, T ₂ << T _P1 ) due to an error in capacitance and resistance and a temperature change. Counter 62
Divides by counting the counting clock when the selection signal is at a high level, and generates a mask signal as shown in FIG. 13D whose half cycle T ₃ is larger than the fluctuation error T ₂ and supplies it to the decoder 68. .

In this case, the decoder 68 is composed of an AND circuit, and when the output of the counter 62 is at high level, FIG.
The signal shown in (F) is supplied to the latch section 96. The latch unit 96 is composed of a D-type flip-flop and is reset at the rising edge of the selection signal output from the selector 90, and then latches the output of the decoder 68 to generate the signals shown in FIGS. Supply to 98.

The mono-multi 98 is for setting the protection time T _{P2. When} the output of the latch unit 70 at the high level is supplied, the mono-multi 98 rises after the substantial protection time T _P2 has passed.
The signal shown in (J) is generated and supplied to the decoder 100. However, the protection time T _P2 has a variation error T ₂ (<< T _P2 ). When the output of the counter 62 is high level, the decoder 100 latches the output of the mono-multi 72 by the take-out latch unit 102 as shown in FIG. 13K and supplies it to the subsequent mono-multi. Note that the latch portion 102 is formed of a D flip-flop like the 96, and after being reset at the rising edge of the selection signal, latches the output of the decoder 100 to generate the signal shown in FIG.

The n-th mono-multi 104 has a protection time T _Pn
When the output of the latch unit at the high level of the preceding stage is supplied, after substantially passing the protection time T _Pn ,
A rising signal is generated and supplied to the decoder 106. However, the protection time T _Pn has a variation error T ₂ (<< T _P2 ). The decoder 106 takes out the output of the monomulti 104 when the output of the counter 62 is at a high level, and outputs it from the terminal 94 through the flip-flop 92. FIG. 14 (A)-
(M) shows the signal waveforms of the respective parts corresponding to FIG. 13 when the clock loss is recovered.

In this way, the protection time (T _P1 + T _P2 + ... T _Pn ) for disconnection detection and disconnection recovery can be extended by connecting the multi-multi, the decoder and the latch unit in cascade, and in this case also disconnection detection and disconnection recovery. The protection time of can be set to an accurate value.
FIG. 15 is a block diagram of a seventh embodiment of the present invention, which detects clock loss and loss recovery with different protection times. In the figure,
A counting clock is input to the terminal 60 and supplied to the counter 110. The clock to be monitored enters the terminal 61 and is supplied to the disconnection detector 64. The disconnection detection unit 64 has a time constant larger than the period Tα of the monitoring target clock, for example, 1.5 × Tα, and the disconnection detection signal S1 that becomes high level when the monitoring target clock does not rise within this 1.5 × Tα period.
Is generated and supplied to the inverter 65 and the selector 90. The inverter 65 inverts the disconnection detection signal S1 and supplies the inverted disconnection detection signal S2 to the selector 90. Selector 90
Selects the signal S1 or S2 by the output of the latch unit 92, generates a selection signal, and outputs the selection signal to the counter 88 and the monomulti 6
Supply to 6.

The mono-multi 66 is for protection against clock loss detection
Interval T_P1For setting the high level selection signal.
Signal is supplied, the protection time T_P1After elapse,
Signal is generated and supplied to the decoder 68. However,
Protective time T kept by Nomulti 66_P1Is the capacity and resistance
Variation error T due to₂(However, T₂≪
T _P1)have. The selection signal of the counter 110 is high
When the level is reached, the counting clock is counted and the
The input value to the decoder 112. Decoder 112
The count value is detected as a disconnection and the mask signal for recovery from disconnection is generated.
And supplies it to the selector 114. The above two mask signals
The half cycle of each is the variation error T of the monomulti 66. ₂Twice the
It is the same as in the other embodiments. Selector 11
4 is a disconnection detection according to the output level of the flip-flop 92
Alternatively, a mask signal for disconnection recovery is selected and supplied to the decoder 68.
To do.

In this case, the decoder 68 is composed of an AND circuit, and when the output of the selector 114 is at high level, it takes out the output of the monomulti 66 and supplies it to the flip-flop 92. The flip-flop 92 is a T-type flip-flop that inverts the output level at the rising edge of the signal output from the decoder 68, generates a disconnection alarm signal, outputs it from the terminal 94, and supplies it to the selector 90.

FIG. 16 is a block diagram of an eighth embodiment of the present invention, which detects a clock break and a break recovery with different protection times. In the figure, a counting clock as shown in FIG. 17A is input to the terminal 60 and supplied to the counter 88. Terminal 6
The clock to be monitored comes into 1 and is supplied to the disconnection detection unit 64. The disconnection detector 64 has a time constant larger than the cycle Tα of the monitored clock, for example, 1.5 × Tα.
The disconnection detection signal S1 which becomes high level when the clock to be monitored does not rise within the 5 × Tα period is generated and supplied to the inverter 65 and the selector 90. The inverter 65 inverts the disconnection detection signal S1 and supplies the inverted disconnection detection signal S2 to the first selector 90. The selector 90 selects the signal S1 or S2 according to the output of the flip-flop 92, and
The selection signal shown in FIG. 7B is generated and supplied to the counter 62 and the monomulti 66.

The mono-multi 66 is for protection against clock loss detection
Interval T_P1For setting the high level selection signal.
Signal is supplied, the protection time T_P1After elapse,
Signal is generated and supplied to the decoder 68. However,
Protective time T kept by Nomulti 66_P1Is the capacity and resistance
Variation error T due to₂(However, T₂≪
T _P1)have. The selection signal of the counter 62 is high
When the bell is turned on,
Go around, half cycle T₃Is the variation error 2 × T₂Larger figure 17
A mask signal as shown in FIG.
Supply.

In this case, the decoder 68 is constituted by an AND circuit, and when the output of the counter 62 is at high level, the output of the monomulti 66 is taken out and supplied to the latch section 96. The latch unit 96 is composed of a D-type flip-flop and is a selector 90.
After being reset at the rising edge of the selection signal output from the output terminal, the output of the decoder 68 is latched and supplied to the monomulti 98.

The mono-multi 98 is for setting the protection time T _{P2. When} the output of the latch unit 70 at the high level is supplied, the mono-multi 98 rises after the substantial protection time T _P2 has passed.
The signal shown in (C) is generated and supplied to the decoder 100. However, the protection time T _P2 has a variation error T ₂ (<< T _P2 ). The decoder 100 takes out the output of the mono-multi 72 when the output of the counter 62 is at a high level, and latches 1
It is latched by 02 and supplied to the subsequent selector 120. The latch unit 102 is composed of a D-type flip-flop like 96, and is reset at the rising edge of the selection signal,
The output of the decoder 100 is latched.

The second selector 120 selects the output of the latch unit 96 upon detection of disconnection according to the output level of the flip-flop 92, and selects the output of the latch unit 102 upon recovery from disconnection and supplies it to the monomulti 104. The mono-multi 104 is for setting the protection time T _Pn , and when the output of the latch unit at the previous stage of high level is supplied, a signal which rises after a substantial protection time T _Pn elapses is generated to generate the decoder 106. Supply to. However, the protection time T _Pn has a fluctuation error T ₂ (<< T _P2 ).
have. When the output of the counter 62 is at a high level, the decoder 106 latches the output of the monomulti 104 by the take-out latch unit 92 as shown in FIG.

In this way, when disconnection is detected, mono-multi
66 and 104 protection time (T _P1+ T_Pn) Is set
When the disconnection is recovered, the monomulti 66, 98 and 104
The protection time is set by, and it is long at disconnection detection and recovery.
The protection time can be different.

FIG. 18 is a block diagram of a ninth embodiment of the present invention for detecting clock loss and loss recovery with different protection times. This embodiment is a combination of the seventh and eighth embodiments. In the figure, a counting clock is input to the terminal 60 and supplied to the counter 110. The clock to be monitored enters the terminal 61 and is supplied to the disconnection detector 64. Disconnection detector 6
4 has a time constant larger than the period Tα of the monitored clock, for example, 1.5 × Tα, and generates a disconnection detection signal S1 which becomes high level when the monitored clock does not rise within this 1.5 × Tα period. And supplies it to the inverter 65 and the selector 90. The inverter 65 inverts the disconnection detection signal S1 and supplies the inverted disconnection detection signal S2 to the selector 90. The selector 90 outputs the signal S1 according to the output of the latch unit 92.
Alternatively, S2 is selected, a selection signal is generated and supplied to the counter 88 and the monomulti 66.

Mono-multi 66 is protected when clock loss is detected
Interval T_P1For setting the high level selection signal.
Signal is supplied, the protection time T_P1After elapse,
Signal is generated and supplied to the decoder 68. However,
Protective time T kept by Nomulti 66_P1Is the capacity and resistance
Variation error T due to₂(However, T₂≪
T _P1)have. The selection signal of the counter 110 is high
When the level is reached, the counting clock is counted and the
The input value to the decoder 112. Decoder 112
The count value is detected as a disconnection and the mask signal for recovery from disconnection is generated.
And supplies it to the selector 114. The above two mask signals
The half cycle of each is the variation error T of the monomulti 66. ₂Twice the
It is the same as in the other embodiments. Selector 11
4 is a disconnection detection according to the output level of the flip-flop 92
Alternatively, a mask signal for disconnection recovery is selected and supplied to the decoder 68.
To do.

In this case, the decoder 68 is composed of an AND circuit, and when the output of the selector 114 is at high level, it takes out the output of the monomulti 66 and supplies it to the latch section 96. The latch section 96 is composed of a D-type flip-flop and is a selector 9
After being reset at the rising edge of the selection signal output by 0, the output of the decoder 68 is latched and supplied to the monomulti 98.

The mono-multi 98 is for setting the protection time T _{P2. When} the output of the latch unit 70 at the high level is supplied, the mono-multi 98 generates a rising signal after the protection time T _P2 has passed. It is supplied to the decoder 100. However, the protection time T _P2 has a variation error T ₂ (<< T _P2 ). When the output of the counter 62 is at the high level, the decoder 100 takes out the output of the monomulti 72 and latches it in the latch unit 102 to supply it to the subsequent selector 120. The latch unit 102 is composed of a D-type flip-flop like 96, and latches the output of the decoder 100 after being reset at the rising edge of the selection signal.

The selector 120 selects the output of the latch unit 96 when the disconnection is detected according to the output level of the flip-flop 92, and selects the output of the latch unit 102 when the disconnection is recovered and supplies it to the monomulti 104. The mono-multi 104 is for setting the protection time T _Pn , and when the output of the latch unit at the previous stage of high level is supplied, a signal which rises after a substantial protection time T _Pn elapses is generated to generate the decoder 106. Supply to.
However, the protection time T _Pn has a variation error T ₂ (<< T _P2 ). The decoder 106 takes out the output of the mono-multi 104 when the output of the counter 62 is at the high level, and latches it 92
It is latched by and is output from the terminal 94.

In this way, when the disconnection is detected, the mono multi
66 and 104 protection time (T _P1+ T_Pn) Is set
When the disconnection is recovered, the monomulti 66, 98 and 104
The protection time is set by, and it is long at disconnection detection and recovery.
The protection time can be different.

FIG. 19 is a block diagram of an embodiment of an optical transmission repeater to which the device of the present invention is applied. In the figure, an optical signal is transmitted through an optical cable 150 to an OR-PKG (optical receiver board) 1
52. The OR-PKG 152 performs optical / electrical conversion of the received optical signal, and the received data after conversion is shown in FIG.
The clock indicated by 0 (A) is extracted. Then, this extracted clock is divided by ⅛ to make it as shown in FIG. 20 (B), and the serial reception data is serial / parallel converted into 8-bit parallel data, and both of them are MD-PKG.
(Information processing board) 154.

The MD-PKG 154 performs descramble after converting the received 8-bit parallel data into 64-bit parallel data in order to further reduce the speed. At this time, the clock is divided by ⅛, as shown in FIG. Then, the overhead portion of the data is rewritten, scrambled again, converted into 8-bit parallel data, speeded up, and supplied to the OS-PKG (optical transmission board) 156. The MD-PKG154 switches to a free-running clock 1 msec after the occurrence of input data interruption, clock interruption, or loss of synchronization, sets all bits to 1 and writes the identification code of its own station in the overhead section.
This data is passed to the OS-PKG 156 together with the 1/8 clock shown in FIG. As a result, the downstream device can know which relay section of the transmission line is disconnected.

The OS-PKG 156 performs parallel / serial conversion on the received 8-bit parallel data and converts it to electrical / electrical data.
The light is converted and sent to the optical cable 158. MD at this time
-1 / received from PKG154 shown in FIG.
The 8 clocks are multiplied by 8 in the OS-PKG 156.

In this case, the clock loss detection time and the clock loss recovery time of the OR-PKG 152 are TA1 and TB1 respectively.
Then, the clock loss detection time and the clock loss recovery time of MD-PKG154 are set to TA2 and TB2, respectively, and OS-PK
When the clock loss detection time and the clock loss recovery time of G156 are respectively TA3 and TB3, TA1 <TA2 <TA
3, and set TB1>TB2> TB3.

Thereby, for example, the OR-PKG152
When a clock loss occurs in the OS, the MD-PKG 154 or the OS-PKG 156 can prevent the clock loss from being detected before the OR-PKG 152.
It is possible to prevent the MD-PKG 154 or the OR-PKG 152 from detecting disconnection recovery before detecting disconnection recovery in G156.

[0066]

As described above, the invention according to claim 1 is
A detection unit that detects at least one of disconnection and recovery of the monitored clock, a delay circuit that outputs a delay signal after a predetermined time including an error after the detection signal of the detection unit is supplied, and the supply of the detection signal After that, a counter that counts the counting clock to generate a mask signal having a time width larger than the error of the delay circuit, and removes the error of the delay signal from the delay signal and the mask signal, and outputs the detection signal as a protection time. And a decoder for outputting.

Therefore, even if the cycle of the counting clock is shortened, the counter only needs to generate a mask signal having a time width larger than the error of the delay circuit, so that the number of flip-flop stages is small and the circuit scale can be reduced. In addition, it is possible to obtain a detection signal with high accuracy and small variation in protection time.

The invention described in claim 2 is the same as claim 1
In the clock monitoring device described above, the delay circuits and the decoders are cascade-connected. This makes it possible to set a long delay time, which is impossible with a single delay circuit, that is, a protection time, and to obtain a detection signal with a small variation in the protection time.

The invention described in claim 3 is the same as claim 1
In the clock monitoring device described above, there is provided a first selector which selectively selects the disconnection detection signal and the disconnection recovery detection signal output by the detection unit and supplies the detection signal to the delay circuit and the counter. The protection time for each detection is the same.

Thus, the delay circuit, the counter, and the decoder can be commonly used for the disconnection detection and the disconnection recovery detection, and the circuit scale can be further reduced. The invention according to claim 4 is the clock monitoring device according to claim 2, wherein the disconnection detection signal and the disconnection recovery detection signal output from the detection section are selected and supplied to the delay circuit and the counter. And a protection time of the disconnection detection and that of the disconnection recovery detection are the same.

As a result, the delay detection and the disconnection recovery detection can share the counter and the delay circuit and the decoder that are connected in multiple stages, and the circuit scale can be further reduced. According to the invention of claim 5, in the clock monitoring device of claim 4, the output signals of different decoders of the multistage cascade connected decoders are switched and selected as detection signals at the time of disconnection detection and at the time of disconnection recovery detection. It has a second selector for outputting.

For this reason, the protection times for the disconnection detection and the disconnection recovery detection can be greatly different, and a part of the circuit can be shared to reduce the circuit scale. In addition, claim 6
The invention according to claim 1 is the clock monitoring device according to claim 1 or 5, wherein the disconnection detection signal and the disconnection recovery detection signal output from the detection unit are selectively selected and supplied to the delay circuit and the counter. The counter has a selector of 1, and the counter generates a mask signal having a different time width when the disconnection is detected and when the disconnection is detected.

Therefore, the protection times for the disconnection detection and the disconnection recovery detection can be made different with high accuracy, and a part of the circuit can be shared to reduce the circuit scale.

[Brief description of drawings]

FIG. 1 is a block diagram of a device of the present invention.

FIG. 2 is a signal timing chart of each part of FIG.

FIG. 3 is a block diagram of the device of the present invention.

FIG. 4 is a signal timing chart of each part of FIG.

FIG. 5 is a block diagram of the device of the present invention.

6 is a signal timing chart of each part of FIG.

FIG. 7 is a block diagram of the device of the present invention.

FIG. 8 is a block diagram of the device of the present invention.

9 is a signal timing chart of each part of FIG.

FIG. 10 is a block diagram of the device of the present invention.

11 is a signal timing chart of each part of FIG.

FIG. 12 is a block diagram of the device of the present invention.

13 is a signal timing chart of each part of FIG.

FIG. 14 is a signal timing chart of each part of FIG.

FIG. 15 is a block diagram of the device of the present invention.

FIG. 16 is a block diagram of the device of the present invention.

FIG. 17 is a signal timing chart of each part of FIG.

FIG. 18 is a block diagram of the device of the present invention.

FIG. 19 is a block diagram of an optical transmission repeater to which the device of the present invention is applied.

FIG. 20 is a waveform diagram of clocks in each unit of FIG.

FIG. 21 is a block diagram of a conventional device.

FIG. 22 is a signal timing chart for explaining FIG. 21.

FIG. 23 is a signal timing chart for explaining FIG. 21.

FIG. 24 is a block diagram of a relay device to which a conventional device is applied.

[Explanation of symbols]

32,62 counter 34, 64 disconnection detector 36,66 Mono-multi (delay circuit) 38,68 decoder 40, 70 Latch part

Claims (6)

(57) [Claims] 1. A detection unit for detecting at least one of disconnection and recovery of a monitored clock, and a delay circuit for outputting a delay signal after a predetermined time including an error after the detection signal of the detection unit is supplied, After supplying the detection signal, a counter that counts the counting clock to generate a mask signal having a time width larger than the error of the delay circuit, and removes the error of the delay signal from the delay signal and the mask signal, A clock monitoring device, comprising: a decoder that outputs the detected signal. 2. The clock monitoring device according to claim 1, wherein the delay circuits and the decoders are connected in cascade. 3. The clock monitoring device according to claim 1, further comprising a first selector which selectively selects the disconnection detection signal and the disconnection recovery detection signal output from the detection unit and supplies the detection signal to the delay circuit and the counter. A clock monitoring device having the same protection time for disconnection detection and protection time for disconnection recovery detection. 4. The clock monitoring device according to claim 2, further comprising a first selector which selectively selects the disconnection detection signal and the disconnection recovery detection signal output from the detection unit and supplies the detection signal to the delay circuit and the counter. A clock monitoring device having the same protection time for disconnection detection and protection time for disconnection recovery detection. 5. A clock selector according to claim 4, wherein the output signals of different decoders of the multistage cascade connected decoders are selectively selected and output as a detection signal at the time of disconnection detection and at the time of disconnection recovery detection. And a clock monitoring device. 6. The clock monitoring device according to claim 1, wherein the disconnection detection signal and the disconnection recovery detection signal output from the detection unit are selectively selected and supplied to the delay circuit and the counter. The clock monitoring device, wherein the counter generates a mask signal having a different time width when the disconnection is detected and when the disconnection is detected.