JP3548942B2 - Frame synchronization circuit - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a frame synchronization circuit, and more particularly to a frame synchronization circuit used for establishing synchronization of a digital multiplex signal.
[0002]
[Prior art]
An example of a conventional frame synchronization circuit will be described. FIG. 2 is a configuration diagram of an example of a conventional frame synchronization circuit.
[0003]
One example of a conventional frame synchronization circuit multiplexes the frame phase of the frame synchronization pattern inserted into the input signal f1 and the frame phase of the frame synchronization pattern generated in the circuit by a one-bit immediate hunting method. And a pulse synchronization circuit 2 having a frame synchronization comparison circuit 1 for comparing only at the conversion position, a YES pulse counting circuit 201 for counting the coincidence of the comparison result, and a NO pulse counting circuit 202 for counting the disagreement. A determination circuit for determining whether the frame is synchronized or asynchronous and transmitting a control signal for controlling the hunting operation of the frame synchronization comparison circuit;
[0004]
Next, the operation of the frame synchronization circuit will be described.
[0005]
The frame synchronization circuit has a timing monitoring counter (not shown) for managing the frame synchronization pattern period, and compares the frame synchronization pattern of the phase generated by the timing monitoring counter with the input signal f1 only at the multiplexing position of the frame synchronization pattern. I do. The coincidence / non-coincidence of the comparison result is counted, and the synchronous state and the asynchronous state are determined based on the result.
[0006]
The synchronization state is a state in which the auxiliary signal can be separated and the main signal can be transmitted because the frame phase of the input signal f1 and the frame phase of the timing monitoring counter are in synchronization.
[0007]
On the other hand, the asynchronous state is a state in which the auxiliary signal cannot be separated and the main signal cannot be transmitted because the frame phase is not established.
[0008]
Therefore, a frame synchronization circuit that realizes signal transmission needs to be able to quickly establish synchronization and maintain the synchronization state.
[0009]
According to FIG. 2, the frame synchronization circuit 1 generates a frame synchronization pattern by the timing monitoring counter and compares it with an input signal to generate a comparison result f2.
[0010]
The pulse counting circuit 2 counts the comparison result f2. When the comparison result f2 matches, the counting is performed by the YES pulse counting circuit 201, and when the comparison result f2 does not match, the counting is performed by the NO pulse counting circuit 202. The YES pulse counting circuit 201 and the NO pulse counting circuit 202 output counting results f3 and f4, respectively, when each counting condition is satisfied.
[0011]
The determination circuit 4 receives the count results f3 and f4 of the YES and NO pulse counting circuits 201 and 202, and outputs a determination result f7 indicating synchronous / asynchronous. When the pulse of f3 is input, f7 indicates synchronous, and when the pulse of f4 is input, f7 indicates asynchronous. Therefore, the synchronization establishment / synchronization holding characteristics are determined by the counting conditions of the YES and NO pulse counting circuits 201 and 202.
[0012]
Hereinafter, the setting conditions of the YES and NO pulse counting circuits 201 and 202 will be described in detail.
[0013]
The number of bits of the frame synchronization pattern in one frame length Nf bits is Fs bit, the counting condition of YES pulse counting circuit 201 is Ny bit continuous coincidence detection, and the counting condition of NO pulse counting circuit 202 is Nn bit or more non-coincidence detection of Rn bit. When (Rn >> Nn), in the synchronization establishment process, when the comparison result does not match, the expected value of the synchronization establishment and synchronization holding period of the frame synchronization circuit having the 1-bit immediate hunting method of performing the comparison by shifting by 1 bit. Is represented as follows:
[0014]
The expected value E1 of the synchronization establishment time is
E1 = ((Pe1 / (1-Pe1)) · Nf / Fs · (Nf−1) + Nf + Ny · Nf / Fs) · 1 / Fr (time) (1)
It is represented by
[0015]
The expected value E2 of the synchronization holding time is
E2 = Nn / Pe2 · Nf / Fs · 1 / Fr (time) (2)
Where Pe1 and Pe2 are error detection probabilities of the comparison result, Nf is one frame length, Ny is the number of consecutive matches of YES for pull-in, Nn is the number of NOs for loss of synchronization, and Fr is the radio clock. The frequency Fs is the number of bits of the frame synchronization pattern in one frame length Nf bits.
[0016]
From equation (1), in order to quickly establish synchronization, the expected value E1 only needs to be small. In other words, it can be seen that this can be realized by reducing the number of bits of Ny.
[0017]
By the way, in the frame synchronization circuit, pull-in is quickly established in order to perform signal transmission quickly. Therefore, as described in detail in the setting conditions of the YES and NO pulse counting circuits 201 and 202, the number of consecutive coincidences Ny of YES for pulling in the synchronization is set to be smaller than the number of bits Fs of the frame synchronization pattern in one frame length Nf bits. I do. Thus, the pull-in can be quickly established. However, in the pull-in establishment in the setting of Fs> Ny, since all bits of one frame synchronization pattern are not monitored, a pseudo pull-in may occur.
[0018]
The pseudo pull-in means that when a signal pattern similar to the frame synchronization pattern multiplexed in the input signal f1 is included in the input signal, the signal pattern is determined to be a normal frame synchronization pattern, and synchronization is established. It is to be.
[0019]
The following is an example. FIG. 5 is a signal format diagram showing a relationship between an input signal and a frame synchronization pattern bit.
[0020]
As an example, in the case where the 1-bit immediate hunting method Fs = 20, the setting conditions of the YES and NO pulse counting circuits 201 and 202 serving as the determination conditions are determined by the YES pulse counting circuit 201 with 10-bit continuous coincidence (Ny = 10). It is assumed that the synchronization is determined, and the setting is made by the NO pulse counting circuit 202 to determine the asynchronous state when there is a mismatch of Nn = 30 bits or more in Rn = 100 (= 5 × Fs).
[0021]
Here, the input signal f1 has a special fixed pattern in which the frame synchronization patterns F11 to F15 are different from the normal frame synchronization pattern at positions different from the normal frame phase, and the other bits are the same as the frame synchronization pattern. It is assumed that a signal including the input is input.
[0022]
At this time, the frame synchronization circuit first detects a 10-bit consecutive match in the bits up to the 10th bit, and determines that synchronization has been achieved. Thereafter, a mismatch is detected from the 11th bit to the 15th bit. However, since only 25 bits (5 times from F11 to F15) can be counted as a mismatch up to 5 × Fs, it cannot be determined that the data is asynchronous, and the synchronous state is maintained. to continue.
[0023]
As described above, there is a drawback that a pseudo pull-in that maintains a synchronization state occurs despite an incorrect frame phase due to a relationship between a YES determination condition for quickly establishing synchronization and a signal pattern of an input signal. .
[0024]
Therefore, a frame synchronization circuit for preventing the occurrence of the pseudo pull-in is disclosed in Japanese Patent Laid-Open No. Hei 4-238435. FIG. 3 is a configuration diagram of a frame synchronization circuit disclosed in this publication, and FIG. 4 is a configuration diagram of a determination circuit included in the circuit.
[0025]
This frame synchronization circuit includes a frame synchronization circuit main body 301 and a determination circuit 302.
[0026]
The frame synchronization circuit body 301 compares the frame phase of the input signal with the frame synchronization pattern of the frame phase generated in the circuit only at the multiplexing position by a 1-bit immediate hunting method, and compares the frame synchronization error pulse 303 with the frame synchronization position. The signal 304 is transmitted.
[0027]
The determination circuit 302 includes an error pulse position determination circuit 311 for transmitting each error pulse at the multiplexing position of the frame synchronization pattern, and error pulse counting circuits 312 to 31n for counting each error pulse (n is a positive integer). And an interval generation circuit 320 for resetting the error pulse counting circuits 312 to 31n and setting the counting range. Further, a control signal 321 is output from the determination circuit 302 to the frame synchronization circuit main body 301.
[0028]
The frame synchronization circuit main body 301 compares the frame synchronization pattern formed on the input signal by the one-bit immediate hunting method with the synchronization signal generated within itself by using the frame synchronization error pulse 331 and the position information of the error pulse. To the determination circuit 302 as an error pulse position signal 332 indicating
[0029]
The operation in the determination circuit 302 will be described. The error pulse position determination circuit 311 receives the frame synchronization error pulse 331 and the error pulse position signal 332, converts them into error signals corresponding to the position of the frame synchronization pulse, and sends out the error signals to the error pulse counting circuits 312 to 31n. . If the frame synchronization pulse is Fs bits, the number of error pulse counting circuits 312 to 31n is Fs.
[0030]
Each of the error pulse counting circuits 312 to 31n is reset by an output signal of the interval generation circuit 320, and counts error pulses starting from the reset. When the counted value exceeds the set threshold value, each of the error pulse counting circuits 312 to 31n outputs a hunting control signal 342 to 34n. These hunting control signals 342 to 34n are all ORed and output to the frame synchronization circuit main body 301.
[0031]
Therefore, if at least one of the Fs error pulse counting circuits 312 to 31n exceeds the set threshold, the hunting control signal 321 is sent to the frame synchronization circuit main body 301. If the hunting control signal 321 is not transmitted, the hunting operation is stopped and synchronization is established. If the hunting control signal 321 is transmitted, the hunting operation is continued and continued until synchronization.
[0032]
[Problems to be solved by the invention]
However, this circuit has a drawback that it takes time to determine the pseudo pull-in and it takes a long time to establish the pull-in. This will be described below.
[0033]
First, it is assumed that the same input signal as that of the conventional example is input to this circuit. The interval in the decision circuit 302 is set to Rn (= 5 × Nf) of one frame length Nf bits or more, and the threshold value for the count value of each of the error pulse counting circuits 312 to 31n (in this case, there are Fs) is set to Nn = It is 5 bits. At this time, during the period up to 5 × Nf, the F11 to F15th error pulse counting circuits count 5 bits each, detect a pseudo pull-in, and return to the pull-in operation again.
[0034]
The problem here is that the error pulse counting circuits 312 to 31n of the present circuit are configured by the number of bits Fs of the frame synchronization pattern in one frame length Nf bits, and each error counting circuit counts only once in one frame. That's what it means. Therefore, at least 5 frames must be monitored to determine the pseudo pull-in under the above conditions. (Because the threshold value is 5 bits, 5 frames are necessary since the first frame to the 5th frame are considered to be inconsecutive.) ).
[0035]
After that, the process returns to the pull-in process again, and even if the normal pull-in is performed, the time for five frames has already been required. As described above, it takes time until the pseudo pull-in determination is made, and it takes time to establish the normal pull-in.
[0036]
SUMMARY OF THE INVENTION It is an object of the present invention to provide a frame synchronization circuit which can reduce the time required for establishing a normal pull-in and can detect a pseudo pull-in.
[0037]
[Means for Solving the Problems]
In view of the above problems, the frame synchronization circuit of the present invention detects a reception frame synchronization pattern from a received digital multiplexed signal , and compares the reception frame synchronization pattern with a reference frame synchronization pattern provided in its own station on a bit-by-bit basis . Thus, a frame synchronization circuit for establishing frame synchronization,
Comparing the corresponding bit data of the plurality of bit data constituting the received frame synchronization pattern with the corresponding plurality of bit data constituting the reference frame synchronization pattern, and detecting a continuous bit data match of a first set number or more. And a comparison result between the reference frame synchronization pattern for n frames (where n is a real number of 2 or more) and the reception frame synchronization patterns, and as a result, the total bit data of a second set number or more is output. A comparing unit configured to output a count result indicating an asynchronous state when a mismatch is detected; a comparing unit configured to output a count result indicating an asynchronous state; and a determining unit configured to determine a synchronous state / asynchronous state based on the count result output from the comparing unit. Comparing the reference frame synchronization pattern with the reception frame synchronization pattern after the counting result indicating the synchronization state is output. If a bit data match equal to or greater than a third set number greater than the first set number is detected, a count result indicating the synchronization state is continuously output, and only bit data matches less than the third set number are detected. A pseudo-pull-in means for outputting a count result indicating an asynchronous state when not performed is provided.
[0038]
Further, the second configuration example of the frame synchronization circuit according to the present invention is characterized in that, in addition to the above-described configuration, the third set number is set to a value smaller than the second set number.
[0039]
Further, in the third configuration example of the frame synchronization circuit of the present invention, in addition to the above-described first or second configuration, a counter shown when only bit data matching less than the third set number is detected. The result is output within a range of m frames (1 ≦ m <n).
[0040]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a configuration diagram of a preferred embodiment of a frame synchronization circuit according to the present invention. The same components as those in the conventional example (FIG. 2) are denoted by the same reference numerals, and description thereof will be omitted.
[0041]
In the frame synchronization circuit according to the present invention, a pseudo pull-in determination circuit 3 is provided at a stage preceding the determination circuit 4 having the conventional configuration (FIG. 2), and the pseudo pull-in counting result f5 and the NO counting result f4 of the output thereof are output by the OR circuit 5. In this configuration, logic synthesis is performed, and the count result f6 is input to the determination circuit 4. When the pulse of f5 or f4 is input, the OR circuit 5 outputs the pulse to f6.
[0042]
The circuits and signals described in the conventional example (FIG. 2) operate similarly.
[0043]
The pseudo pull-in determination circuit 3 has the same function as the YES pulse counting circuit 201, and counts the coincidence of the comparison result f2.
[0044]
This circuit 3 is a circuit provided to determine whether or not the frame synchronization pattern determined to be synchronized by the counting result of the YES pulse counting circuit 201 is a normal frame phase. During (for example, once), the total number of coincidences of Fs bits or more is counted.
[0045]
Thus, a 5-bit error of F11 to F15 occurring in the conventional example is detected, and a pulse is detected at f5. The count result f5 is ORed with the count result f4 by the OR circuit 5, and the count result f6 is input to the determination circuit 4. When the determination circuit 4 determines that the pseudo pull-in operation is performed, the determination result f7 pulse indicates an asynchronous state, and the synchronization is established again.
[0046]
The counting range of the pseudo pull-in determination circuit is as follows: YES pulse count circuit count range <pseudo pull-in determination circuit count range <NO pulse count circuit count range. This is a circuit that counts coincidence during the synchronization pattern or more.
[0047]
Also, as for the threshold value for the count value, a feature of the pseudo-pull-in state is that a mismatch is output fixedly. It is possible to determine a pseudo pull-in that could not be determined, and to quickly determine a pseudo pull-in.
[0048]
For example, the input signal f1 similar to the conventional example (FIG. 2), that is, the frame synchronization pattern bits F1 to F10 and F16 to F20 are regular frame synchronization patterns, but the frame synchronization pattern bits F11 to F15 are regular frame synchronization patterns. The case where a signal different from the above is input will be described.
[0049]
The determination conditions of the YES pulse count circuit 201 and the NO pulse count circuit 202 are the same as in the case of the conventional example (FIG. 2).
[0050]
At this time, the setting condition of the pseudo pull-in determination circuit 3 is determined to be asynchronous by a match of 40 bits or less out of 50 bits (2.5 × Fs) , that is, a match of 41 bits or more is counted in order to be determined as synchronous. It is assumed that the condition is set as a condition.
[0051]
In this case, since the input signal f1 matches 15 bits (frame synchronization pattern bits F1 to F10 and F16 to F20) of the frame synchronization pattern bits of the total of 20 bits, 50 bits (2.5 × Fs) are counted. In the first 20 bits (the number of bits Fs of the frame synchronization pattern in one frame length Nf), 15 bits match, 15 bits of the second 20 bits match, and the third 10 bits (in this case, Is 0.5 × Fs, so that 20 × 0.5 = 10 (bits).) 10 bits (that is, frame synchronization pattern bits F1 to F10) match.
[0052]
The sum of this match is 15 + 15 + 10 = 40 . Accordingly, the number of matches is not counted for 41 bits or more, and the determination circuit 4 determines that it is asynchronous, and the synchronization is established again.
[0053]
As described above, according to the present invention, pseudo pull-in determination is performed from pull-in, and it takes only 3.5 frames (10-bit continuous coincidence + 50-bit pseudo determination) until pull-in is performed again.
[0054]
【The invention's effect】
According to the present invention, the number of matches is counted again by the third counting means after the matching determination is made by the determining means, and the count value of the third counting means is set to the threshold value (the threshold value in this case is the first value). When the count value is less than the threshold value, the frame synchronization circuit is configured to be determined as asynchronous when the count value is less than the threshold value. Therefore, a pseudo synchronization pattern can be detected. Further, since the first threshold can be set to a value less than the number of bits constituting the frame synchronization pattern, the time required for establishing the normal pull-in can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a frame synchronization circuit according to a preferred embodiment of the present invention;
FIG. 2 is a configuration diagram of an example of a conventional frame synchronization circuit.
FIG. 3 is a configuration diagram of a frame synchronization circuit disclosed in Japanese Patent Application Laid-Open No. 4-238435.
FIG. 4 is a configuration diagram of a determination circuit included in the circuit.
FIG. 5 is a signal format diagram showing a relationship between an input signal and a frame synchronization pattern bit.
[Explanation of symbols]
1 frame synchronization comparison circuit 2 pulse counting circuit 3 pseudo pull-in determination circuit 4 determination circuit 5 OR circuit

Claims (3)

A frame synchronization circuit for detecting a reception frame synchronization pattern from a received digital multiplexed signal and comparing the reception frame synchronization pattern with a reference frame synchronization pattern provided in the own station on a bit-by-bit basis, thereby establishing frame synchronization. ,
Comparing the corresponding bit data of the plurality of bit data constituting the received frame synchronization pattern with the corresponding plurality of bit data constituting the reference frame synchronization pattern, and detecting a continuous bit data match of a first set number or more. And a comparison result between the reference frame synchronization pattern for n frames (where n is a real number of 2 or more) and the reception frame synchronization patterns, and as a result, the total bit data of a second set number or more is output. Comparing means constituted by a coincidence / mismatch counting means for outputting a count result indicating an asynchronous state when a mismatch is detected;
Determining means for determining a synchronous state / asynchronous state based on the counting result output from the comparing means;
After the counting result indicating the synchronization state is output, the reference frame synchronization pattern and the reception frame synchronization pattern are compared, and a bit data match of a third set number or more larger than the first set number is detected. In this case, pseudo-pull-in means for continuously outputting a count result indicating a synchronous state, and outputting a count result indicating an asynchronous state when only bit data matching less than the third set number is detected, is provided. Characteristic frame synchronization circuit. The frame synchronization circuit according to claim 1, wherein the third set number is set to a value less than the second set number. 2. The method according to claim 1, wherein the counting result indicated when only the bit data coincidence less than the third set number is detected is output within a range of m frames (1 ≦ m <n). 3. The frame synchronization circuit according to 2.

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