JPH0691514B2 - Bit string match determination circuit - Google Patents

Description

The present invention relates to a bit string coincidence determination circuit, and in particular, it is obtained by comparing two bit strings including bit errors with a small probability such as transmission bit errors bit by bit. The present invention relates to a bit string match determination circuit that determines whether or not bit strings are the same based on a bit match determination signal.

[Conventional technology]

Such a bit string coincidence determination circuit is often required in electronic devices that handle data. A conventional bit string coincidence determination circuit will be described by taking as an example the case of use for line switching of a digital microwave communication system having a protection line.

Two data (data A, data A, respectively) transmitted in parallel by the working circuit and the protection line of the digital microwave communication system
B) does not necessarily have the same bit phase due to a propagation delay difference between the working line and the protection line. Moreover,
Since the propagation delay difference fluctuates with time, the bit phase shift between the data A and B also fluctuates with time. When the working line and the protection line are switched when the bit phases do not match, a bit error occurs at the time of switching. To avoid the occurrence of this bit error, the bit phase detection circuit determines whether the bit phases of data A and B match, and if they do not match, the relative bit phases are forcibly shifted to match and then Switch the line.

FIG. 2 is a block diagram showing a first example of the bit phase detection circuit.

The bit phase detection circuit shown in FIG. 2 is an exclusive OR circuit (hereinafter referred to as EX-OR) 1 that inputs data A and B and outputs a bit match determination signal C, and a conventional one that inputs the bit match determination signal C. The bit string coincidence determination circuit 2 of FIG.

EX-OR1 outputs "0" if the two inputs match, and outputs "1" if they do not match. Therefore, data A and B are compared bit by bit, and a match / mismatch judgment result is output. Operates as a bit comparison circuit.

If the bit phases of the data A and B are in agreement and there is no transmission bit error, the bit coincidence determination signal C is continuous "0". However, it may be "1" due to transmission bit error. If the bit phases of the data A and B do not match, the bit match determination signal C is usually "1" with a high probability.
become.

The bit string match determination circuit 2 counts the number of times the bit match determination signal C becomes “0” and the number of times it becomes “1” for each predetermined period, and based on these count values, the data A and B are counted.
Matches or disagrees with. This determination result is used as the output determination output.

However, when the data A and B are lightly loaded and there is almost no bit change component, the probability that the bit match determination signal C becomes "1" becomes small even if the bit phases do not match. For example, assuming that data A and B include one frame synchronization bit of "1" in one frame of 2928 bit length and all other bits are "0" (excluding transmission bit error), data A and B When the bit phases of B and B do not match, the probability that the bit match determination signal C becomes "1" is 2/2928.
It becomes a small value of ≒ 7 × 10 ^-4 . In this case data A,
When the transmission bit error rate of B becomes about 7 × 10 ⁻⁴ , it cannot be distinguished whether the bit coincidence determination signal C becomes “1”, the bit phase mismatch, or the transmission bit error. The bit phase detection circuit shown often malfunctions.

FIG. 3 is a block diagram showing a bit phase detection circuit of a second example proposed so that it can be used without malfunction even at a higher transmission bit error rate.

The bit phase detection circuit shown in FIG.
Two serial conversion units 3 that input B and output bit strings A _{1 to} A ₁₆ and B _{1 to} B ₁₆ , and bit strings Ai and Bi (i is 1 to 1).
16 integer) and outputs the bit match determination signal Ci 16
EX-OR1, 16 bit string match judging circuits 2 each of which inputs a bit match judging signal Ci and outputs a bit string match judging signal Di, and an OR circuit (inputs the bit string match judging signals D _{1 to} D ₁₆ 4).

The serial-to-parallel converter 3 divides the data A and B into 16 and outputs 1
Converts to 6 bit strings A _{1 to} A ₁₆ , B _{1 to} B ₁₆ . By this conversion, one time slot of the bit string A _{1 to} A ₁₆ , B _{1 to} B ₁₆ is 16 times as long as one time slot of the data A and B,
Assuming that the data A and B include 2928 bits in one frame period, the bit strings A _{1 to} A ₁₆ and B _{1 to} B ₁₆ are 2 in the same one frame period.
Including 928/16 = 183 bits. Two serial-parallel converters 3
Divides the bits of the data A and B in the same time slot so as to be arranged in the same time slot of the bit strings A _{1 to} A ₁₆ and B _{1 to} B _{16 in} the same order and in synchronization with each other.

Each EX-OR1 consists of bit string A _{1 to} A ₁₆ and bit string B _{1 to} B.
Columns in the same order as ₁₆ are compared bit by bit, and bit match determination signals C _{1 to} C ₁₆ are output. If the bit phases of data A and B match, bit string A _{1 to} A ₁₆ and bit string B _{1 to} B
₁₆ means that the bit phases of the columns in the same order match each other except the transmission bit error, so that the bit matching determination signals C _{1 to} C ₁₆
Are all consecutive "0" except for transmission bit error.
If the bit phases of the data A and B do not match, the bit strings A _{1 to} A ₁₆ and the bit strings B _{1 to} B ₁₆ do not match in the same order, so the bit match determination signals C _{1 to} C ₁₆ 1 "occurs.

Each of the bit string match determination circuits 2 has a bit string A _{1 to} A ₁₆ and a bit string B _{1 to} B ₁₆ based on the bit match determination signals C _{1 to} C _16.
Matching or non-matching between the columns in the same order as ₁₆ is judged, and bit string matching judgment signals D _{1 to} D ₁₆ which are “0” when they match and “1” when they do not match are output.

Data A, because if bit phase and B they match the bit string matching determination signal D ₁ to D ₁₆ all become "0", the judgment output is the output signal of the OR4 becomes "0". If the bit phases do not match, at least two of the bit string match determination signals D _{1 to} D ₁₆ become “1”, and the determination output becomes “1”.

The bit phase detection circuit shown in FIG. 3 determines whether or not the bit phases of the data A and B coincide with each other by 16 bit string coincidence determination signals D _{1 to} D ₁₆ , and the information for the determination is shown in FIG. Since the number of bit phase detection circuits is relatively large as compared with the bit phase detection circuit shown in FIG.

Now, the data A, when each bit of B is to become all but the frame synchronization bit of a "1" in one frame period (except for transmission bit errors) "0", the bit string A ₁ to A _16,
B ₁ .about.B appear one bit "1" only in one frame period in each one row of the _16, the other bits are all "0". In this case, if the bit phases of the data A and B do not match, the bit strings A _{1 to} A ₁₆ and the bit strings B _{1 to} B ₁₆ do not match only in two sets having the same order, and the bit string match determination signal D Two of _{1 to} D ₁₆ become “1”. in this case,
Since the probability of "1" appearing in the bit string including the frame synchronization bit is 1/183 ≈ 5.5 × 10 ^-3 , the transmission bit error rate of data A and B is about 5.5 × 10 ^-3 , as shown in Fig. 3. The bit phase detection circuit often malfunctions.

As described above, the bit phase detection circuit shown in FIG. 2 frequently malfunctions with a transmission bit error rate of about 7 × 10 ^-4 , whereas the bit phase detection circuit shown in FIG. Since it often malfunctions at a transmission bit error rate of about × 10 ^-3, it can be used without malfunction even at a higher transmission bit error rate.

FIG. 4 is a block diagram showing an example of a conventional bit string match determination circuit 2.

In the conventional example shown in FIG. 4, a negation circuit (hereinafter referred to as NOT) 11 that inputs a bit coincidence determination signal Ci, a first NO counter 12 that inputs a bit coincidence determination signal Ci and outputs a pulse P ₁ , and N
A first YES counter 13 that receives the output signal of the OT 11 and outputs a pulse P ₂ and NAND circuits (hereinafter referred to as NAND) 16 and 17 are configured. The NAND 16 inputs the pulse P ₁ and the output signal of the NAND 17, and outputs a bit string coincidence determination signal Di. NA
ND17 inputs the pulse P ₂ and the output signal of NAND16.

The operation of the conventional example shown in FIG. 4 will be described below assuming that it is used in the bit phase detection circuit shown in FIG.

The first NO counter 12 sets the bit coincidence determination signal Ci to “1” every 5 frame synchronization of the data A and B (every 183 × 5 bits of the bit strings Ai and Bi) (in units of the time slot length of the bit strings Ai and Bi). The number of times is counted, and when the count value reaches 4, a negative pulse P ₁ is output. The first YES counter 13 is a bit string
A ₁ ~A _16, B ₁ NOT11 output signal of every 16 bits of .about.B ₁₆ becomes "1" (bit match determination signal Ci is "0") and counts the number of times, the count value is reach the 12 Then, the negative pulse P ₂ is output.

NAND16,17 is because they are mutually connected with a pulse P ₂ is set at the pulse P ₁ as RS type flip-flop is reset, the bit string matching determination signal Di is, when the pulse P ₁ is inputted "1", the pulse P ₂ When is input, it becomes "0".

When the transmission bit error of the bit strings Ai and Bi can be ignored, if the bit strings Ai and Bi match, the bit match determination signals Ci all become “0”, so the pulse P ₁ does not occur and the pulse P ₂ occurs. The bit string match determination signal Di becomes "0". If the bit strings Ai and Bi do not match and the bit match determination signal Ci becomes "1" at least once within one frame period, a pulse P ₁ is generated every 5 frame periods. It becomes "1". Since the pulse P ₂ may occur even if the bit strings Ai and Bi do not match, when the pulse P ₂ occurs, the bit string match determination signal Di becomes “0” until the next pulse P ₁ occurs.

As described above, in the conventional example shown in FIG. 4, if the bit match determination signal becomes "1" even once in one frame, the mismatch between the bit strings Ai and Bi can be detected. Therefore, if the bit coincidence determination signal Ci is erroneously output about once per frame due to a transmission bit error, a malfunction occurs. The malfunction probability decreases as the transmission bit error rate decreases, but does not decrease rapidly. Therefore, if a small malfunction probability is required, the transmission bit error rate (3 × 10 ^-4) occurs once in one frame. Can be used only with a transmission bit error rate sufficiently smaller than

[Problems to be solved by the invention]

As described above, in the conventional bit string match determination circuit, the probability of malfunction due to the stochastic error of the bit match determination signal does not sharply decrease due to the decrease in the error rate of the bit match determination signal. It has the drawback that it cannot be used unless the rate is very small.

An object of the present invention is to provide a bit string coincidence judging circuit in which the probability of malfunction is sharply reduced by reducing the error rate of the bit coincidence judging signal.

[Means for solving problems]

The bit string coincidence judging circuit of the present invention counts, for each first period, the number of times that the judgment result of the bit comparison means for comparing two bit strings for each bit to judge whether or not they coincide with each other. A first counting unit that outputs a first pulse when the count value reaches a first threshold value, and the number of times that the determination result indicates a match is counted for each second period that is shorter than the first period. Second counting means for outputting a second pulse when the count value reaches a second threshold value, and the first pulse for each third period that is twice or more the first period. Third counting means for counting and outputting a third pulse when the count value reaches the third threshold value; and for counting the second pulse, the first count value is the first pulse of the second pulse. If the fourth threshold is exceeded that is greater than the maximum number of possible occurrences during Is output and is cleared by the first pulse, and when the third pulse is input, the first state is taken out of two states, and when the fourth pulse is input, the two states are output. 2 of which takes the second state
And a logic circuit means for outputting a value coincidence determination signal.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the drawings illustrating an embodiment.

FIG. 1 is a block diagram showing an embodiment of a bit string coincidence judging circuit of the present invention.

The embodiment shown in FIG. 1 is configured by adding a second NO counter 14 and a second YES counter 15 to the conventional example shown in FIG. The second NO counter 14 receives the pulse P ₁ and receives the pulse P ₃
Is output to NAND16. The second YES counter 15 outputs the pulses P ₁ , P
Input ₂ and output pulse P ₄ to NAND17.

The same use conditions as used in the description of the conventional example shown in FIG.
That is, the two bit strings that have obtained the bit match determination signal Ci form one frame with 183 bits, and if the bit strings do not match each other, the bit match determination signal Ci is "1" at least once within one frame period. The operation of the embodiment shown in FIG. 1 will be described under the use condition of ".

The second NO counter 14 outputs a pulse P every 5 × 16 frame periods.
_The number of times ₁ is input is counted, and when the count value reaches 14, a negative pulse P ₃ is output. The second YES counter 15 counts the number of times the pulse P ₂ is input, generates a negative pulse P ₄ when the count value reaches 92, and is cleared when the pulse P ₁ is input (the count value becomes 0). Become). As described above, the counting period of the first NO counter 12 is 5 frames, and the maximum number of pulses P ₂ that can be generated during this counting period is 5 × 183/16 <58.
Is. The count threshold of the second YES counter 15 is set to 92, which is larger than 58.

When the probabilistic error of the bit match determination signal Ci can be ignored, if the bit strings that have obtained the bit match determination signal Ci match, pulse P ₁ does not occur, and as a result, pulse P ₃ does not occur. On the other hand, a pulse P ₂ is generated every 16 bits,
Since the pulse P ₄ is generated every 16 × 92 bits (about 8 frames), the bit string coincidence determination signal Di becomes “0” and never becomes “1”. If the bit strings do not match, 5
A pulse P ₁ is generated for each frame, and the number of occurrences is 16 in 5 × 16 frames, so a pulse P ₃ is generated and the bit string coincidence determination signal Di becomes “1”. On the other hand, the 2YES counter 15 is cleared by the occurrence of pulses P _1, no pulse P ₄ is generated because the maximum number of pulses P ₂ generated by the pulse P ₁ is then generated 58 or less and less than 92. Therefore, if the bit strings do not match each other, the bit string match determination signal Di continues to hold "1".

When the error rate of the bit match determination signal Ci becomes about 5.5 × 10 ⁻³ , the pulse P ₁ is generated even if the bit strings match each other. However, the probability that the pulse P ₃ is generated by the occurrence of erroneous pulses P ₁ is small and the probability of false generation of the pulse P ₃ when the probability of erroneous generated pulses P ₁ decreases sharply decreases. Therefore, the error rate of the bit match determination signal Ci is
If it becomes slightly smaller than 5.5 × 10 ^-3 , the probability of false occurrence of pulse P ₃ becomes extremely small, and the bit string match determination signal
The probability that Di will be "1" by mistake is extremely small.

As described above, the embodiment shown in FIG. 1 can be applied to a light load bit string in which the bit match determination signal Ci becomes "1" only once in one frame (183 bits) when the bit strings do not match each other. Until a mismatch can be detected and the error rate of the bit match determination signal Ci approaches 5.5 × 10 ⁻³ , the probability of erroneously determining a mismatch as a mismatch is extremely small.

When the embodiment shown in FIG. 1 is used in the bit phase detection circuit shown in FIG. 3, the transmission bit error rate of data A and B is 5.5 × 10 ^−3.
It is possible to judge the coincidence and non-coincidence of the bit phase extremely accurately until the deterioration is caused to some extent.

In the embodiment shown in FIG. 1, the first YES counter may be cleared when the pulse P ₂ is generated, and the next measurement may be started immediately. By doing so, the determination time can be shortened. Also at this time, the maximum number of pulses P ₂ (5 × 183/12 <77) in the counting period (5 × 183 bits) of the first NO counter 12 is smaller than the counting threshold (92) of the second YES counter 15. is necessary. Further, the second NO counter can be cleared by the pulse P ₄ . By doing this, the second NO counter always starts counting from 0 when the bit strings change from coincidence to disagreement.
The certainty of ₃ improves.

〔The invention's effect〕

As described above, the bit string match determination circuit of the present invention is
By determining the frequency of occurrence of the first pulse (pulse P ₁ ) by the third counting means (second NO counter), the probability of malfunction will decrease sharply if the error rate of the determination result of the bit comparison means decreases. Therefore, even if the error rate of the determination result of the bit comparison means deteriorates, there is an effect that it is possible to determine whether the bit strings match or do not match very accurately until the malfunction frequently starts, and by the first pulse. Since the generation of the fourth pulse (pulse P ₄ ) is prohibited, there is also an effect that when the bit strings do not match, no determination result indicating the match is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a bit string coincidence judging circuit of the present invention, and FIGS. 2 and 3 are first and second examples of a bit phase detecting circuit which is an application example of the bit string coincidence judging circuit. FIG. 4 is a block diagram showing an example, and FIG. 4 is a block diagram showing an example of a conventional bit string match determination circuit. 11 …… NOT (Negation circuit), 12 …… First NO counter, 13 ……
1st YES counter, 14 ... 2nd NO counter, 15 ... 2nd YES
Counter, 16, 17 ... NAND (Negative product circuit).

Claims (1)

[Claims] 1. The number of times that the determination result of a bit comparison unit that determines whether or not there is a match by comparing two bit strings for each bit is counted every first period and the counted value is A first counting unit that outputs a first pulse when the threshold value of 1 is reached, and a count value obtained by counting the number of times that the determination result indicates a match for each second period that is shorter than the first period. Second counting means for outputting a second pulse when the second threshold value is reached; and counting and counting the first pulse for each third period that is at least twice the first period. Third counting means for outputting a third pulse when the numerical value reaches a third threshold value, and counting value of the second pulse is possible in the first period of the second pulse. If a fourth threshold value larger than the maximum number of occurrences is reached, a fourth pulse is output and the first pulse is output. A fourth counting means which is cleared by a pulse; and when the third pulse is input, the first state of the two states is taken, and when the fourth pulse is input, the second state of the two states is taken. And a logic circuit means for outputting a binary match determination signal.