JPS62128634A - Detecting circuit for abnormality of clock signal - Google Patents

Abstract

PURPOSE:To detect the abnormal state of a PM clock signal by detecting the disconnection of the 2nd clock signal while a phase modulated clock signal of the 1st frequency is transmitted by means of the 2nd clock signal of the 2nd frequency. CONSTITUTION:A signal state output circuit 115 holds the logic state of the 2nd clock signal 111 of a frequency f1 for a prescribed period in response to the timing of the 2nd clock signal 113 of a frequency f2(>f1) which is used for transmission of the signal 111. A signal state detecting circuit 119 detects the signal state in response to the output signal of the circuit 115. The 2nd clock abnormality detecting circuit 121 detects the abnormal state of the signal 113 and produces a detection output signal 125. An abnormality deciding circuit 127 decides the abnormality of the signal 111 in response to the output signals of both circuits 119 and 121. In such a constitution, the abnormal state of the signal 111 is detected through the total constitution of an abnormality detecting circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A clock signal abnormality detection circuit, for example, when a phase modulated (PM) clock signal of a first frequency f1 has a second frequency f1.
a(>f+), the discontinuation of the second clock signal is detected, and P
It becomes possible to detect an abnormal state of the M-took signal.

[Industrial application field]

The present invention relates to a clock signal abnormality detection circuit, and more particularly, the present invention relates to a clock signal abnormality detection circuit that detects an abnormal state of a PM check signal when the PM check signal is being transmitted using a clock signal of a different frequency, for example. It is related to.

For example, in the field of communications, a technology is widely used in which one clock signal is transmitted using a clock signal with a higher frequency than another clock signal. In particular, in subscriber line terminal equipment, the PM check signal is transmitted using another clock signal with a higher frequency, and the PM check signal is in an abnormal state, that is, disconnection, or the encoding is "high".
Alternatively, a feature is provided to detect the persistence of a "low" logic state. There is a need for a device that can reliably detect such an abnormal state of the PM check signal.

[Conventional technology]

The PM Tsukku signal with a repetition frequency of 400flz is 8
There is a circuit that transmits data using a MHz clock signal (hereinafter referred to as a second clock signal). Here, a signal state output circuit that outputs the signal state of the PM check signal using a second clock signal, and a "logic state detection circuit" whose input signal is the output of each stage of flip-flops forming the circuit are provided. Based on these detected logic states, an abnormal state of the PM check signal is detected.

[Problem that the invention seeks to solve]

However, in such a conventional abnormal state detection method, since the second clock signal of 8M1lz is used as one input signal to the signal state output circuit, the second clock signal is
When the clock signal is not transmitted normally, the flip-flop in the signal status output circuit malfunctions. Therefore, there is a problem in that it is not possible to reliably detect particularly when the PM check signal is in an abnormal state other than the continuation of the encoded "high" logic state or "low" logic state.

The present invention was created in view of the above points, and an object of the present invention is to provide a clock signal abnormality detection circuit that can detect an abnormal state of a clock signal with a simple configuration.

[Means for solving problems]

FIG. 1 is a principle block diagram of a clock signal abnormality detection circuit according to the present invention.

In FIG. 1, the signal state output circuit 115 has a frequency of 1
1, the logic state of the first clock signal 111 is determined by the frequency f2 (〉f,
) is held for a predetermined period of time in accordance with the timing of the second clock signal 113.

The signal state detection circuit (119) is the signal state output circuit 115
detecting the signal state in response to the output signal of the

The second clock abnormality detection circuit 121 detects an abnormality in the signal state of the second clock signal 113 and generates a detection output signal 125.

The abnormality determination circuit 127 is connected to the signal state detection circuit 119 and the second
In response to the output signal of the clock abnormality detection circuit 121, the first
Determine whether the clock signal is abnormal.

Therefore, the entire configuration is adapted to detect a signal abnormality of the first clock signal 111.

[Effect]

The first clock signal 111 is transmitted by the second clock signal 113, and the second clock signal 113 has a higher frequency (f2>r).

Depending on the timing of the second clock signal 113, the logic state of the first clock signal 111 is determined by the signal state output circuit 115.
is output from. A detection signal 123 from the signal state detection circuit 119 responsive to the output indicates the presence or absence of an abnormality in the signal state.
is generated.

If the second clock signal 113 does not take the original signal state but becomes abnormal, the second clock abnormality detection circuit 121 generates a detection signal 125.

An abnormality determination circuit 127 responsive to these detection signals performs an abnormality determination, and an abnormality in the first clock signal 111 is detected based on a signal 129 representing the result.

In the present invention, by providing the second clock abnormality detection circuit 121 that detects the signal abnormality state of the second clock signal 113, it is possible to detect the signal abnormality state of the first clock signal 111 without using a complicated circuit configuration. becomes possible.

〔Example〕

FIG. 2 shows an embodiment of the invention. Here, the frequency f1 of the PM clock signal 211 is 400 Iz, and the frequency f2 of the second clock signal 213 for transmitting this is 8 Mllz.

The PM check signal state output circuit 215, which is driven by the second clock signal 213 based on the logic state of the PM check signal 211, is similarly constructed by cascading three stages of flip-flops, and outputs a logic signal every clock in the second clock signal 213. The logic state of the PM pull signal 211 is maintained for a plurality of pulses of the clock by outputting the state. Three-bit output signals 221 and 223 representing the signal state of the PM check signal state output circuit 215 are supplied to a first logic state detection circuit 225 and a second logic state detection circuit 227, respectively.

The first logic state detection circuit 225 is composed of three Nandt gates, and the first logic state detecting circuit 225 is a logic "low" state and takes a bell only when the signal states of all three bits forming the output signal 221 are "high" logic level. A detection signal 231 is generated.

The second logic state detection circuit 227 is made up of three OR gates, and the second logic state detecting circuit 227 assumes a "low" logic level only when the signal states of all three bits forming the output signal 223 are at a "low" logic level. A detection signal 233 is generated.

The change point detection circuit 241 receives the output signal 243 of the PM check signal state output circuit 215 and detects the signal 243.
A change point detection signal 2 that changes state when there is a transition from a “low” logic state to a “high” logic state or vice versa.
45 is generated.

The second clock disconnection detection circuit [i'&251 generates a clock disconnection detection signal 253 that outputs a "low" logic level when the second clock signal 213 is disconnected.

First detection signal 231. The logical product output signal 263 of the ant game 1261 that logically ANDs the second detection signal 233 and the change point detection signal 245 is logically ANDed by an AND gate 265 that is separate from the clock interruption detection signal 253 . The logical AND output signal 267 is supplied to the discrimination circuit 269.

The first detection signal 231 is inverted by an inverter 271, and then ANDed by the clock loss detection signal 253 and the anti-gate 273, and a first logic signal 275 is output.

After the second detection signal 233 is inverted by another inverter 277, the clock loss detection signal 253 and the antgame 1 are inverted.
-279 and the second logic signal 28
1 is output.

Figure 3 (al ~ (CI Ll) shows various signals in the circuit of Figure 2. However, the time scales do not match,
Some parts have been enlarged for clarity.

Here, the PM click signal 211 will be explained.

Generally, as means for generating the PM signal, one exclusive OR gate is used as shown in FIG. Signal a carrying a high” logic state or a “low” logic state as a sign
and a signal responsible for general transmission are applied to this exclusive OR gate. Then, a PM signal is obtained as the output of this gate. .

Such signal states are illustrated by (A) to (C) in FIG. now. Assume that the signal a shown in Figure (A) is at the same low logic level as "0" to be encoded. Also, the signal A shown in Figure (B) is as shown in Figure (B). For example, it is assumed that the signal is a 4MIIz rectangular wave signal.

As shown in the figure (C), the output of the exclusive OR gate causes a level transition from "high" to "low" and from "low" to "high" when the signal a is 10. As shown in FIG. NaP
The M signal is applied as the PM check signal 211 in FIG.

Next, the operation of the embodiment of the present invention configured as shown in FIG. 2 will be explained.

Now, the PM signal as described in Figs. 4 and 5 is P
As the M clock signal 211 and the second clock signal 2
13 are both applied to the PM pull signal status output circuit 215.

The PM check signal 211 is as shown in FIG. 3 fbl.
“High”, “low”, “high°゛,” “high”, “high”.

Assume that the signal pulse train becomes as follows. This signal 2
Since it is clocked by the second clock signal 213 when a level transition occurs in P.11, that is, depending on the sign, P
The first stage flip-flop of the M-took signal state output circuit 215 maintains its code content of "high" or "low" logic state.

In response to one pulse of the next PM check signal 211, it is transmitted to the next stage flip-flop. Therefore, the three successive logical states of the PM check signal 211 are held in the PM check signal state output circuit 215.

When the time corresponding to 3 pulses of the PM check signal 211 has elapsed from the time when both the 3 flip-flops and the flip-flops of the PM check signal status output circuit are reset to the initial state, the three flip-flops become "high" in order. , "low" and "high" logic states are maintained.The PM clock signal status output circuit 215 has two output signals 221 and 2.
Assuming that 23 is a signal representing the held logic state of the three flip-flops at 11TI, the first logic state detection circuit 22
5 and the first output from the second logic state detection circuit 227
Both the detection signal 231 and the second detection signal 233 are at a "high" logic level.

Furthermore, when the time corresponding to two pulses of the PM check signal 211 has elapsed, the holding logic states of the three flip-flops of the PM check signal state output circuit 215 are changed to "high" (■) and "
High (■), “high” (■) (see Figure 3 fbl)
. Therefore, the first detection signal 231 of the first logic state detection circuit 225 becomes a "low logic" level, and the inverter 271
is inverted and becomes a “high” logic, which becomes a bell and un1 gate 2
73. Here, if the second clock signal 213 comes normally, the clock loss detection signal 253 of the second clock loss detection circuit 251 is at a "high" logic level. Therefore, the first logic signal 275 having a "high" logic level is generated from the ant gate 273, and the encoded logic state of the PM check signal 2+1 is "high", "high", "high",
“It can be determined that there was a continuous high.

Similarly, if the encoded logic state of the PM check signal 211 continues as "low", "low", and "low", the second
Second detection signal 2 output from logic state detection circuit 227
33 becomes a "low" logic level, and the AND gate 279 generates a second logic signal 281 that is "high" and takes a bell, so it is determined that the "low" logic state has continued for three pulses. be done.

By the way, it is assumed that the change point detection circuit 241 uses, for example, the charging and discharging characteristics of a capacitor, and inverts the level when the discharging time extends beyond a predetermined time. In such a circuit, the PM pull signal 211 (2
43), the "low" logic level of the PM check signal 211 will be prolonged if the "high" logic state transitions to the "low" logic state, so the level inversion circuit will change the "low" logic level as shown in FIG. 3 fcl. A change point detection signal 245 is generated that is at a "low" logic level for a predetermined period of time.

Now, the change point detection signal 245 is detected according to the timing relationship shown in the figure.
If the logic level of becomes “low”, during that time the AND gate 2
The output signal 263 of 61 and the output signal 267 of the next ant game 1-265 become a "low degree" logic level.

The determination circuit 269 that receives the AND output signal 267 that takes the "low" level determines whether the "low" level is due to a transition in the logic state of the PM check signal 211. A discrimination signal 270 is generated which takes a "high" logic level if the cause is due to the above, and a "low" logic level if the cause is caused by something else.

Here, the reason why the AND output signal 267 becomes a "low" logic level is because of the first detection signal 231 and the second detection signal 233.
Alternatively, this is the case when the clock loss detection signal 253 becomes a "low" logic level. The above-mentioned distinction is made by the discrimination circuit 269, for example, based on the difference in time.

Thus, a continuing event of a "high" logic state in the PM cook signal 211 is caused by the first logic signal 275.
Further, a continuation event of a "low" logic state is determined by the second logic signal 281, respectively.

Furthermore, it is possible to determine whether or not the encoded logic state has changed in the PM check signal 211 using the determination signal 270 output from the determination circuit 269.

Furthermore, the occurrence of an abnormal state (for example, disconnection) in the second clock 213 for transmitting the PM check signal 211 means that
This can be determined based on the clock interruption detection signal 253.

〔Effect of the invention〕

As described above, according to the present invention, with an extremely simple configuration, even if the signal state of the separate long signal for transmitting the PM check signal becomes abnormal, the PM check signal can be appropriately transmitted. transmission abnormalities can be detected, which is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram showing a clock signal abnormal state detection circuit of the present invention, FIG. 2 is a configuration block diagram showing an embodiment of the present invention, and FIG.
Figures Fal~ (C1 is a signal explanatory diagram, Figure 4 is an explanatory diagram of the PM signal generation means, and Figures 5 (A) to (C) are explanatory diagrams of the PM signal. In Figure 1, 111 is the first 113 is a second clock signal; 119 is a signal state detection circuit; 121 is a second clock abnormality detection circuit; 127 is an abnormality determination circuit. In FIGS. 2 and 3, 211 is a PM check signal; 213 is the second clock signal, 231 is the first detection signal, 233 is the second detection signal, 245 is the change point detection signal, 253 is the second clock disconnection detection signal, 1, 5 275 is the first logic signal, 281 is the second detection signal It is a logical signal.

Claims (1)

[Claims] The logic state of a first clock signal (111) with a frequency f_1 is set to a frequency f_1 for transmitting the first clock signal.
a signal state output circuit (115) that holds for a predetermined period according to the timing of a second clock signal (113) of 2 (>f_1); and a signal state output circuit (115) that responds to the output signal (117) of the signal state output circuit (115). A signal state detection circuit (119) that detects the signal state by
), a second clock abnormality detection circuit (121) that detects an abnormality in the signal state in the second clock signal (113), and an output signal ( an abnormality determination circuit (127) that determines whether the first clock signal (111) is abnormal in response to the first clock signal (123, 125); 1. A clock signal abnormality detection circuit, characterized in that it is configured to define an abnormality in one clock signal.