JPS60236532A - Error detection system - Google Patents

Abstract

PURPOSE:To attain detection of an error signal even in case the errors are produced even times by transmitting the information showing the state of a parity counter of the transmission side in addition to a parity pulse at the transmission side and comparing the conventional parity check with the state of the parity counter at the reception side. CONSTITUTION:When an input data train shown by (a) in the figure is transmitted from the transmission side, the output of a 1.0 counter circuit 1 is shown by (b). A state monitor circuit 5 for counter circuit is set in an output state of (c) since the output of the circuit 1 is used as the input of the circuit 5. Therefore a parity pulse adds ''0'' when an odd parity system is applied. While a pulse ''0'' is added for transmission since the output train obtained by adding ''0, 0'' to the (a) is received at the reception side and then supplied to the circuit 1 and a parity pulse extractng circuit 3. In this case, the output of the circuit 1 of the reception side is shown by (b) with the state of the circuit 5 shown by (c) respectively. Thefore it is possible to detect the presence or absence of an error signal by checking through a comparator 6 whether or not an additional signal is euqal to ''0, 0''.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for detecting errors in signals by parity checking, which is used in digital communication devices and the like.

(b), Conventional technology In digital communication equipment, etc., the transmitting side adds a parity pulse to the information to be transmitted and sends it out, and the receiving side detects erroneous signals by performing a parity check on the received signal. is a commonly used method.

(C)0 Problems to be Solved by the Invention FIG. 3 is a diagram showing an example of a conventional parity check.

In the figure, ■ is a 1/0 counting circuit, 2 is a parity pulse insertion circuit, 3 is a parity pulse extraction circuit, and 4 is a comparison circuit. The same symbols represent the same objects throughout the following discussion.

On the transmitting side, input data is input to a 1/0 counting circuit 1 and a parity pulse insertion circuit 2.

Taking the case of odd parity as an example, 1.0
Counting circuit 1 counts input data by a specified number of bits,
The result is “1” when the output of 1/0 counting circuit 1 is 1.
Since there is an even number of signals, the parity pulse insertion circuit 2 adds a "1" pulse, and when the output of the zero counting circuit 1 is 0, it means that there was an odd number of "1" signals. Therefore, the parity pulse insertion circuit 2 adds a "0" pulse and sends it out.

On the receiving side, the signal to which the parity pulse has been added is received, and a 1/0 counting circuit 1 and a parity pulse extraction circuit 3
Enter. A 1/0 counting circuit 1 counts received data by a prescribed number of bits, and a parity pulse extraction circuit 3 extracts a parity pulse from the received data. 1/0 counting circuit 1
When the output of is 1, it means that there was an even number of "1" signals, so the parity pulse extraction circuit 3 must receive a "1" parity pulse, so the comparator circuit 4 detects a match. If they match, it is determined that there is no erroneous signal, and if they do not match, it is determined that there is an erroneous signal.

As is well known, the parity check method described above can detect an erroneous signal when an error occurs only once, but it cannot detect when an error occurs an even number of times. Each transmitting and receiving side of a digital signal is equipped with a counter that counts the parity information of the digital signal, and the transmitting side adds the parity information and transmits it, and the receiving side calculates the parity information from the received digital signal using the counter. This error detection method detects a parity error by comparing the parity information sent from the transmitting side with the parity information sent from the transmitting side. In this case, the discrimination result of the discrimination means is added to the digital signal as additional information and transmitted, and the receiving side compares the transmitted additional information with the discrimination result of the discrimination means on the receiving side. This is achieved through an error detection method.

(e) 0 effect According to the present invention, as is clear from the above configuration, information indicating the status of the parity counting counter on the transmitting side is sent in addition to the parity pulse, so the receiving side performs a parity check in addition to the conventional parity check. Furthermore, since the states of the parity counters can be compared, an erroneous signal can be detected even if an error occurs an even number of times.

(f), Embodiment FIG. 1 is a block diagram showing an embodiment of the error detection method according to the present invention.

FIG. 2 is a diagram for explaining the operation of FIG. 1.

In the figure, 5 is a state monitoring circuit for the counting circuit, and 6 is a comparison circuit. In FIG. 1, the state monitoring circuit 5 of the counting circuit is 1.
The same divide-by-2 circuit as 0 counting circuit 1 is used.

The present invention will be described in detail below with reference to the drawings.

It is assumed that the input data string shown in ■ in Fig. 2 is sent from the transmitting side. The input data string shown in ■ in Figure 2 consists of 24 bits, and by applying this input data string, the
The output of the counting circuit 1 is as shown in (■) in FIG.

However, it is assumed that the l/0 counting circuit 1 changes at the rising edge of the input pulse.

Since the output of the 1/0 counting circuit 1 is input to the counting circuit state monitoring circuit 5, the output state is as shown in (2) in FIG.

Therefore, if an odd parity method is adopted, "0" is added to the parity pulse. Also, the output of the status monitoring circuit 5 is “0”.
”, an additional “'O” pulse is sent.

On the receiving side, the input data string in which "0.0" is added to the box (2) in FIG.

At this time, the output of the 1/O counting circuit 1 on the receiving side becomes as shown in ■ in Fig. 2, and the output of the counting circuit status monitoring circuit 5 becomes the second one.
It becomes ■ in the figure.

Therefore, in the comparator circuit 6, the presence or absence of an erroneous signal can be detected by checking whether the additional signal is "0, O".

■ in FIG. 2 indicates an input data string with two errors as indicated by the arrows.

In this case, the output of the 1/0 counting circuit 1 on the receiving side is shown in Figure 2.
The output of the state monitoring circuit 5 of the counting circuit becomes as shown in FIG. Although the sent additional signal is "O1θ", the output of the 1.O counting circuit 1 is "0" and does not change, but the output of the counting circuit status monitoring circuit 5 is "l".
This indicates that an erroneous signal was received.

(A) Effects of the Invention As described in detail above, the present invention has the great effect of realizing an error detection method that can detect an erroneous signal even when an error occurs an even number of times.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of an error detection method according to the present invention. FIG. 2 is a diagram for explaining the operation of FIG. 1. FIG. 3 is a diagram showing an example of a conventional parity check. In the figure, ■ is a 1.O counting circuit, 2 is a parity pulse insertion circuit, 3 is a parity pulse extraction circuit, 4 is a comparison circuit, 5 is a status monitoring circuit of the counting circuit, and 6 is a comparison circuit. No. 1 Hi No. 2 Side Qi 3 Fig.

Claims (1)

[Claims] Each of the transmitting and receiving sides of a digital signal is equipped with a counter that counts the parity information of the digital signal. This error detection method detects a parity error by comparing the parity information sent from the transmitting side with the parity information sent from the transmitting side. In this case, the discrimination result of the discrimination means is added to the digital signal as additional information and transmitted, and the receiving side compares the transmitted additional information with the discrimination result of the discrimination means on the receiving side. An error detection method characterized by: