JPH02100549A - Transmission control equipment - Google Patents

Abstract

PURPOSE:To normally transmit data without re-wiring even if there is the mistake of wiring, in which a polarity is inverted by inverting a reception bit pattern when the mistake cannot be recognized even if a flag sequence is checked for several times. CONSTITUTION:When wiring is normally connected, a data route change over switch part 5 is directly connected to a data reception control part 2 as shown in a lower half part, and the data reception control part 2 operates similarly as usual. When a transceiver 3 and a receiver 4 are wired with the polarity being inverted as shown in an upper half part, bit data transmitted from a transmission control part 1 is inverted from the receiver 4 and outputted. The data reception control part 2 switches the data route change over switch part 5 to a bit inversion operation part 6-side and operates is so that data can be received.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a flag-synchronized transmission control device in a transmission system that utilizes voltage polarity for signal encoding.

(Prior Art) Generally, a transmission system that uses voltage polarity for signal encoding has a relatively simple circuit and can increase transmission distance and transmission speed at low cost.

It is also relatively resistant to noise, so it is used in a variety of ways as a transmission means within factories.

Figure 4 shows a conventional transmission control device of this type.
In the figure, (1) is a data transmission control unit, (2) is a data reception control unit, (3) is a transceiver that encodes one bit of data into two output voltages, and (4) is one bit that is encoded from two voltages. It is a receiver that decodes it into data.

The conventional transmission control device is configured as described above, and the (+) and (-) terminals of the transceiver (3) and receiver (4) are connected to the same poles. and,
A data transmission control unit (1) is connected to the input of the transceiver (3).
If there is bit data 1 or O from the transceiver (3
) is the output (+) pole) High voltage or Low voltage,
It converts into a voltage signal with the LOwTL voltage or the old gh voltage with the output (+) pole inverted to the output (-) pole, and transmits it. On the other hand, the receiver (4) has an input (+) pole.

It decodes the High voltage and Low voltage that enter the input (-) pole, and outputs bit data 1 or 0 to the data reception control section (2).

By the way, in the flag synchronous method, data is constructed by adding special bit patterns called flag sequences to the leading and trailing ends of a transmission block called a frame. This bit pattern is checked to establish frame synchronization, and the data reception control unit (2) shown in Fig. 3
is in charge of it.

FIG. 5(A) shows the bit pattern of the frame format, and FIG. 5(B) shows the bit pattern of the flag sequence. The data reception control unit (2) always waits for the arrival of a bit pattern that matches the flag sequence (lO), and does not receive data until the flag sequence (10) comes, and the received bit pattern is the flag sequence. If it matches (10), the subsequent bit data is received as data in the information section (11) of the frame.

[Problem to be solved by the invention]

Conventional transmission systems are configured as described above, and the polarity of the voltage is used to encode the signal, and although there are many mistakes in wiring with the polarity reversed, it is important to note that the wiring connection is normal. If there is a wiring error, the wiring work must be redone, and in places where the wiring is complicated, such as in factories, or where transmission lines are run underground or through pipes, There was a problem in that the wiring could not be easily rewired.

This invention was made to solve this problem, and the object is to provide a transmission control device that can automatically detect wiring polarity errors and transmit data normally without rewiring. shall be.

[Means to solve the problem]

A transmission control device according to the present invention includes a data transmission control means for outputting data with a flag sequence added to the leading and trailing ends of a transmission block, an encoding means for converting the data into a voltage signal, and a voltage signal from the encoding means. a decoding means for returning the voltage signal to the original data; a determining means for comparing a bit pattern of a flag sequence of data from the decoding means with a predetermined bit pattern to determine whether they match or not; and the determining means data means for receiving data from the decoding means in response to input of a coincidence signal from the decoding means; bit inverting means for inverting each bit of data from the decoding means; and a counting means for counting the number of times of determination by the determination means. And when the number of judgments of the counting means reaches the set value,
A path switching means for inputting data from the decoding means to the determining means via the bit inverting means is arranged in a membrane-like manner.

[For production]

In this invention, if the flag sequence cannot be recognized, the bit pattern is inverted and the presence or absence of the flag sequence is checked again. Therefore, a wiring error in which the polarity is reversed is detected and corrected, and data can be transmitted normally without rewiring.

〔Example〕

FIG. 1 is an overall configuration diagram showing an embodiment of a transmission control device according to the present invention. As is clear from FIG. 1, this embodiment includes a data transmission control means (21) that outputs data with a flag sequence added to the leading and trailing ends of a transmission block, and converts the data into a voltage signal. Encoding means (22) and encoding means (22)
Decoding means (23
), and the determining means (24) compares the bit pattern of the flag sequence of the data from the decoding means (23) with a predetermined bit pattern to determine whether they match or not. The means (25) is configured to receive data from the decoding means (23) when a coincidence signal is input from the determining means (24), and furthermore, each of the data from the decoding means (23) is bit inverting means (26) for inverting bit data; and the determining means (24).
) counting means (27) for counting the number of judgments made by
are respectively provided, and when the number of determinations by the counting means (27) reaches a set value, the path switching means (28) transfers the data from the decoding means (23) to the bit inverting means (26). The information is configured to be input to the determining means (24). That is, data from the decoding means (23) is normally input directly to the determining means (24), but if the flag sequence cannot be recognized,
The signal is configured to be input to the determining means (24) via the bit inverting means (26).

FIG. 2 is a hardware configuration diagram showing the transmission control device used in the embodiment of FIG. 1, and in the figure, the same reference numerals as in FIG. 4 indicate the same or corresponding parts.

(5) is a data path changeover switch section for switching between a normal path and a bit inversion path, and (6) is a bit inversion operation section for inverting bit data.

Next, the operation of the above embodiment will be explained with reference to FIGS. 2 and 3. FIG. 3 is a flowchart showing the procedure of data reception.

When the wiring is connected normally, the data path changeover switch section (5) is directly connected to the data reception control section (2), as shown in the lower half of Figure 2, and the data reception control section (2) operates in the same way as before.

On the other hand, as shown in the upper part of Fig. 2, the transceiver (3
) and the receiver (4) are wired with opposite polarities, the bit data transmitted from the data transmission control section (1) will be inverted and output from the receiver (4). That is, bit data “1” transmitted from the data transmission control unit (1) is received as bit data “0” by the data reception control unit (2), and bit data “0” is received as bit data “°1°”. It will be received.

Therefore, in this case, the data reception control section (2) switches the data path changeover switch section (5) to the bit inversion operation section (6).
It operates so that data can be received by switching to the side.

That is, first, in step (31) shown in FIG. 3, the bit pattern of the data obtained from the receiver (4) is compared with the bit pattern of the flag sequence (10). Then, in step (32), it is determined whether both bit patterns match. If they match, the data is received in step (36) as usual, but if the polarity is reversed and both bit patterns do not match, then in step (33) it is determined that the flag sequence check has failed. The number of times is counted, and in step (34) it is determined whether this count exceeds a set value n. Then, the flag sequence check is repeated until the set value n is exceeded.

If the number of times the flag sequence is checked exceeds the set value n, in step (35), an instruction to change the route is issued to the data route changeover switch unit (5), and the data from the receiver (4) is bit-inverted. The data is input to the data reception control section (2) via the operation section (6).

As a result, each bit data of the data inverted by the receiver (4) is again inverted by the bit inversion operation section (6) to become normal bit data, and then transmitted to the data reception control section (2).

Next, the process returns to step (31) again to check the flag sequence, and when a match is found in step (32), data reception is performed (step (36)).

〔Effect of the invention〕

As explained above, in this invention, if the flag sequence cannot be recognized even after checking the predetermined number of times, the received bit pattern is inverted. This has the advantage that data can be transmitted normally without having to be re-transmitted.

[Brief explanation of the drawing]

Fig. 1 is an overall configuration diagram of a transmission control device showing an embodiment of the present invention, Fig. 2 is a hardware configuration diagram thereof, Fig. 3 is a flowchart showing the data reception procedure, and Fig. 4 is a conventional transmission control device. A diagram equivalent to Figure 2 showing the device, Figure 5 (A),
(B) is an explanatory diagram showing a frame format and a flag sequence in a flag synchronization transmission method. (21)...Data transmission control means, (22)...Encoding means, (23)...Decoding means, (24)
...determination means, (25) ...data reception means, (2
6)...Bit inversion means, (27)...Counting means, (28)...Route switching means. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] Data transmission control means for outputting data with a flag sequence added to the leading and trailing ends of the transmission block, encoding means for converting the data into a voltage signal, and returning the voltage signal from the encoding means to the original data. A decoding means, a determining means for comparing a bit pattern of a flag sequence of data from the decoding means with a predetermined bit pattern to determine whether they match or do not match, and inputting a match signal from the determining means, data receiving means for receiving data from the decoding means;
bit inverting means for inverting each bit data of the data from the decoding means; a counting means for counting the number of times of determination by the determining means; A transmission control device comprising path switching means for inputting the data to the determination means via the bit inversion means.