JPS62231341A - Information processor - Google Patents

Abstract

PURPOSE:To specify a troubled data sending circuit and data transmission circuit by adding an identifier generating circuit to a data sending circuit besides a parity generating circuit. CONSTITUTION:Data I from a data register 1b is supplied through a selector 5 to a data receiving register 7a. Simultaneously, a parity I from a parity generating circuit 2 is supplied through a selector 6 to a parity receiving register 8a and an identifier I from an identifier register 1a is supplied through a selector 10 to an identifier receiving register 11a respectively. Data II from a data register 3b, a parity II from a parity generating circuit 4 and an identifier II from an identifier register 3a are also supplied respectively to the corresponding register. Consequently, a parity checking circuit 9 checks the parity, simultaneously, by confirming the waveform of the identifier, it can be specified whether the abnormality exists at a data sending circuit 1 and a transmission circuit D1 or the abnormality exists at a sending circuit 3 and a transmission circuit D2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device that can identify a failure location within the information processing device, particularly a failed data transmission circuit or data transmission circuit.

[Conventional technology]

FIG. 2 is a block diagram showing a conventional information processing device.

Figure [In, (sENI)), (XTRM').

(REcV) are information sending means, information transmitting means,
It is a means of receiving information. The information sending means (rsEND) includes a first data sending circuit (/A) including a first data register (/b) that holds data elements of information (hereinafter simply referred to as data), and this first data sending circuit (/A). a first parity generation circuit (,2) for generating a parity 1 child (hereinafter simply referred to as parity) of data connected to the output side of A) and held in the first data register (/b);
Also, a second data sending circuit (3b) including a first data register (3b) which holds different data with exactly the same cross member as these
3A) and a second parity generation circuit [lIl are arranged in parallel.

The information transmission means (XTRM) has a first data register (/
b) and a data selector (5) which is a two-man power/output selector connected to the output side of the first data register (3b).
In addition, a parity selector (A), which is a two-man/output selector, is connected to the output sides of the first parity generation circuit (C) and the second parity generation circuit (R). The information receiving means (REcV) includes a data receiving circuit (7) including a data receiving register (7a) connected to the output side of the data selector Tel and receiving data selected by the data selector (rl), and a parity selector (B). ) is connected to the output side of the parity receiving register (6) and receives the parity selected by the parity selector (6).
A parity receiving circuit (A'l) including a data receiving circuit (a) and a parity receiving circuit (a'l) is connected to the output side of each of the data receiving circuit (a) and a parity receiving circuit (a'l), and a It consists of a parity check circuit (W) that performs a parity check.
/) is the first data transmission circuit that runs from the first data transmission circuit (/A) to the data reception circuit (RI) through the data selector (s), and (DU) is the second data transmission circuit (3A). ) from the data selector (s) to the data receiving circuit (7).

A conventional information processing device is configured as described above, and the data sent from an external circuit and held in the seventh data register (/b) (this is referred to as data I) or the co-data register (3b) The data held in (this will be referred to as data 2) is transmitted to the data receiving register (RIa) via the data selector (5). Similarly, the first
The output of the parity generation circuit (2) or the output of the second parity generation circuit [lIl is transmitted to the parity reception register (ga) via the harrity selector (6). Here, when the data I is selected by the data selector (5), the select (4') interlocking mechanism INTL selects the interlocking terminals (ja) (6) of the data selector (S) and the parity selector (6), respectively.
a) is operated at the same time, and the parity corresponding to the data ■ is transmitted from the first parity generation circuit (2) to the parity receiving register (fa) through the parity selector (LE). If there is an abnormality in the data transmission between the first data register (/b) and the data receiving register (7a), or between the co-data register (3b) and the data receiving register (7δ), the parity check circuit (?) Generates abnormality detection output.

[Problem that the invention seeks to solve]

Conventional information processing devices have problems in that they do not know from which data sending circuit the data received in the data reception register (7a) has been sent out, and when an abnormality is detected, all the data is treated as a candidate for the abnormality. Since the sending circuit and the data transmission circuit must be taken into account, there are problems in that the target for failure analysis becomes larger, and the replacement range becomes wider when replacing a defective circuit.

This invention was made to solve the above-mentioned problems, and it is possible to identify abnormal data transmission circuits and data transmission circuits, facilitate failure analysis, and localize circuits that should be replaced. The purpose is to obtain an information processing device that can perform the following steps.

[Means for solving problems]

an information transmitting means configured from a plurality of transmitting circuits for holding and transmitting seven sets of information consisting of parity factors and parity factors; and a plurality of sets of information transmitted from the information transmitting means. An information transmitting means for selecting at least a predetermined set of information from among the information, and if an abnormality is found by checking the parity factor of the small predetermined set of information selected by the information transmitting means, an identifier is sent from the information receiving means. An information processing apparatus characterized in that an abnormality has occurred in a data factor transmission circuit which reads out a factor and which data factor transmission circuit extends from the data factor transmission circuit to the information reception means through the information transmission means. be.

[For production]

In this invention, since the data is transmitted and the identifier of the data sending circuit is also transmitted, the data receiving circuit can easily identify the source of the received data, and the parity check circuit can detect errors in the received data. Embodiment FIG. 1 is a block diagram showing an embodiment of an information processing apparatus of the present invention. At π in FIG. 1, (lb).

(s), (3b), (lI), (s), (sex'>A
t, ), (t, et), (q).

(7a), (g), (ga), (9), (DI) and r
I) 2) is exactly the same as the above conventional device6 (
/a) is a first identifier register that stores an identifier factor (hereinafter simply referred to as an identifier) for identifying data I;
It is included in the first data/identifier sending circuit Cc together with the (l)/data register (lb). Similarly, (, 3a) is the data ■
It is a second identifier register that stores an identifier for identifying the first data register (/a) and is included in the first data/identifier sending circuit (71) together with the second data register (3b). This is an identifier selector as a two-man power/output selector connected to the output side of the two-identifier register (3a), and its interlocking terminal (10a) is connected to the interlocking terminal (
sa) and (6a) together with the selector interlocking mechanism (INTL
) is combined with

(//a) is an identifier receiving register connected to the output side of the identifier selector (10) and receiving the identifier selected by the identifier selector (10), and is included in the identifier receiving circuit (//).

In the information processing device configured as described above, when a command is issued to transmit the data currently held in the first data register (lb), that is, data ■ to the data receiving register (7a), the data Selector (jl is data■
At this time, by synchronizing the interlocking (A') terminals (5a), (6a) and (10a) of the selector interlocking mechanism (INTL), the parity selector (6) The identifier selector (10) selects the identifier I sent from the first data identification circuit (2), and the identifier selector (10) selects the identifier I sent from the first data identification circuit (2). Data receiving circuit in the information receiving means (XTRM) +71,
/<The utility receiving circuit Ct1 and the identifier receiving circuit (//) send the data from the information sending means (8END) to the corresponding data receiving register (7ak). , attribute I, and identifier I, respectively.

Furthermore, when a command is issued to send the data held in the 82 data register (3b), that is, the data ■ to the data receiving register (7a), the data ■ in the first data register (3b) and the second parity generation circuit ( Select the identifier II of the first identifier register (3a) using the data selector (r), the identifier selector (6), and the identifier selector (10), respectively, and select the data receiving register (7).
, the parity receiving register (ffl) is received and held in the identifier receiving register (//a).Thus, for example, if data I is desired and selected, then this data is If the parity I of The waveform of the identifier ■ of the data ■ is confirmed by a waveform observation device (not shown).
Is there an abnormality in the data/identifier sending circuit (1) and the first data transmission circuit (D/), or is there an abnormality in the second data/identifier sending circuit (3) and the first data transmission circuit (Ds)? can be identified.

Although the above embodiment shows an example of data transmission from one data/identifier sending circuit to seven data receiving circuits, this method can also be applied to data transmission from a large number of data/identifier sending circuits to a large number of data receiving circuits. The invention can be easily applied.

In addition, when the identifier is transmitted from N data identifier sending circuits to seven identifier receiving circuits, 1" log, 2N
It can be expressed in j bits.

When the outputs of a plurality of data/identifier sending circuits are mixed by an adder/subtractor or the like in a data transmission circuit, it is necessary to use a concatenation of a plurality of identifiers as an identifier.

〔Effect of the invention〕

This invention adds a circuit for generating a new identifier to the information sending means, adds a circuit for selecting and transmitting an identifier to the information transmitting means, and installs a circuit for receiving the identifier and outputting it to the logout bus in the information receiving means. By doing so, the system is configured so that it is possible to identify which data register the data is sent from, so it is possible to limit the target for failure analysis when a failure occurs.
Further, there is an effect that a malfunctioning data register and its data transmission circuit can be identified, and that the number of defective replacement units is also reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an information processing device showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional information processing device. In FIG. 1c, (SEND) is an information sending means, rXTR
M) is the information transmission means, (RECV) is the information receiving means, r
INTL) is the selector interlocking mechanism, (1) is the data/identifier sending circuit, (/a) is the first identifier register, (lb)
is the first data register, (2) is the first parity generation circuit, (3) is the second data/identifier sending circuit, (3a) is the first identifier register, and (3b) is the first data register %(
(51) is a data selector, (6) is a parity selector, (wa) is a data receiving circuit, (ria) is a data receiving register, (g) is a parity receiving circuit, (ga) is a Parity reception register, (9) is parity check circuit, (yO) is identifier selector,
(//) is an identifier receiving circuit, and (iih) is an identifier receiving register. (/2) is the output line, (/3] is the logout bus, (D/
) is the first data transmission circuit, and (D) is the first data transmission circuit. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (4)

[Claims] (1) Information sending circuit that is composed of a plurality of sending circuits that hold and send out a set of information consisting of a data factor, an identifier factor that identifies this data factor, and a parity factor of the data factor, and sends out multiple sets of information. means, information transmitting means for selecting at least a predetermined set of information from among the plurality of sets of information sent from the information transmitting means, and receiving the at least predetermined set of information selected by the information transmitting means. comprising information receiving means for checking, and if there is an abnormality by checking the parity factor of the predetermined set of information, reading the identifier factor from the information receiving means and determining which data factor sending circuit and from which the data factor sending circuit the said information is detected; An information processing apparatus characterized in that it is determined whether an abnormality has occurred in a data factor transmission circuit that passes through a transmission means and reaches the information reception means. (2) The information sending means includes a sending circuit including a data register that holds a data factor and an identifier register that holds an identification factor of the data factor, and a parity generating circuit that generates a parity factor based on the data factor. An information processing device according to claim 1. (3) The information transmission means has a data selector, a parity selector, and an identifier selector for inputting a plurality of sets of information data factors, parity factors, and identifier factors from a plurality of sending circuits for each same factor, and these The selectors are interlocked with each other, and when a predetermined set of information is selected and output, each factor of the corresponding set is output from the corresponding selector, and the selected set of factors is sent to the information receiving means. A plurality of sets of information processing apparatuses according to claim 1. (4) The information receiving means includes a data receiving circuit including a data receiving register for storing a data factor, a parity receiving circuit including a parity receiving register for storing a parity factor, a parity check circuit for checking the parity factor, and an identifier. 2. The information processing apparatus according to claim 1, comprising an identifier receiving circuit including an identifier receiving register for storing factors.