JPH02228748A - Data transfer system - Google Patents

Abstract

PURPOSE:To exactly point out a fault spot when an error is generated in transfer data by checking the reading data of a buffer provided in a data transmitter and sending a checked result to a data receiver together with the transfer data. CONSTITUTION:An error detection circuit 14 checks the error to the respective transfer data read from a data buffer area 11, which is operated regardless of a clock (a,) and sends error information 903 to a data receiver 2 when the error is detected. An error reception circuit 24 sets the error information 903 of transfer data 904 sent from the error detection circuit 14 in an internal part at the same timing with the transfer data 904 according to a clock (b.) When the error is generated, the generation of the error is informed of a diagnostic device. Namely, when the error information 903 show '1', information 202 are sent to the diagnostic device and it is registered that a data buffer 11 has the fault. Then, the exchange of the relevant part is instructed. Thus, concerning the transfer data, the cause of the error can be pointed out more exactly.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transfer system, and more particularly to error detection in transferred data.

When trying to transfer a large amount of data at high speed between devices that operate using clocks that are asynchronous to each other, it is difficult to transfer data one by one using the well-known interlock method. Since this was not possible, the following data transfer was performed.

First, multiple pieces of transfer data can be stored in the device that is sending the data, a write instruction and write address are given in synchronization with the clock of the sending device, and a read address is sent from the device receiving the data to the receiving device. Provide a buffer that is provided in synchronization with the clock.

Next, the data to be transferred is temporarily written to the buffer with a parity bit added to detect errors in the data, and after the sending device issues a data transfer request, the receiving device writes the data to the buffer. A read address was given, the transfer data was read out along with the parity bit, and the data was set in a register within the receiving device. Furthermore, the parity bit is used to check for errors in the transferred data stored in the register.

In other words, the above-described method for detecting errors in transfer data involves checking the transfer data for errors after the transfer data is once set in a register within the receiving device.

However, in such error detection methods, when an error is detected, it is difficult to determine whether the cause of the error is in the buffer in the sending device, in the register in the receiving device, or on the interface between the sending device and the receiving device. Since it is difficult to determine the error, it takes a lot of time to find the cause of the error.

1. Summary of the Invention An object of the present invention is to provide a data transfer system that can more accurately identify the cause of an error in transferred data.

A data transfer system according to the present invention is a data transfer system comprising a data sending device including a storage means for storing a plurality of data to be transferred, and a data receiving device receiving the data. an error detection means provided in the exit device to detect the presence or absence of an error in each of the plurality of data; and an error detection means provided in the data reception device to receive the data and the detection results of the error detection means for the data in correspondence with each other. It is characterized by having a receiving means for.

K shin 1 Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of a data transfer system according to the present invention. In FIG.
and a data receiving device. Note that the data sending device 1 operates in synchronization with a clock a sent from an internal clock generator 10, and the data receiving device 3!2 operates in synchronization with a clock b sent out from an internal clock generator 20. It is something to do.

The data sending device 1 includes a clock generator 1o, a data buffer 11, a write address circuit 12, a data sending control circuit 13, and an error detection circuit 14.

The data buffer 11 can store 2N pieces of transfer data to which parity bits have been added, and when a read address is given, the transfer data can be read out regardless of the clock a.

The write address circuit 12 creates a write address and provides the write address 104 to the data buffer 11.

The data transmission control circuit 13 instructs 1 to write transfer data 101 to the data buffer 11 in response to a data transfer instruction 100.
02 and also sends operation instruction 1 to the write address circuit 12.
03 and further sends a data transfer request 900 to the data receiving device 2.

The error detection circuit 14 is a data buffer 1 consisting only of a gate circuit (not shown) that operates independently of the clock a.
A device that checks for errors using parity bits that are read simultaneously for each transfer data read from 1, and sends an error report 903 to the data receiving device 2 if an error is detected as a result of the check. It is.

In addition to the tarok generator 20, the data receiving device 2 also includes a tarok generator 20,
It is configured to include a data buffer 11, a data reception control circuit 21, a read address circuit 22, an error reception circuit 24, and a transfer data reception register 25.

The read address circuit 22 creates a read address for the data buffer 11 and sends it to the data sending device 1.

The data reception control circuit 21 provides an operation instruction 200 to the read address circuit 22 in response to a data transfer request 900 from the data transmission device 1.

The transfer data reception register 25 is set with transfer data 904 read from the data buffer 11.

The error receiving circuit 24 internally sets an error report 903 of the transfer data 904 sent from the error detection circuit 14 at the same timing as the transfer data 904 using clock b, and reports it to the diagnostic device when an error occurs. be.

In the data transfer system having such a configuration, the operation will be described when data is transferred between devices having different operating clocks from the data sending device 1 to the data receiving device 2.

When the data sending device 1 intends to transfer data, it inputs a data transfer instruction 100 to the data sending control circuit 13. Then, the data sending control circuit 13 supplies the write address 104 to the data buffer 11 at the same time as the write instruction 102 by giving an operation instruction 103 to the write address circuit 12 .

In this case, the write address 104 is sequentially added starting from address 0, so that the transfer data 101 with parity pits added is sequentially stored in the data buffer 11.

When the storage of the transfer data 101 in the data buffer 11 is completed, the data sending ITJ control circuit 13 is loaded! 2, a data transfer request 900 is sent. When the data receiving device 2 receives the data transfer request 900 in the data receiving control circuit 21, the data buffer 11 in the data transmitting device 1 responds to the data transfer request 900.
An operation instruction 200 is given to the read address circuit 22 in order to read the transfer data stored in the . Then, the read address circuit 22 sequentially adds the read address 901 starting from address O and sends it to the data sending device 1.

When the data exit device 1 receives the read address 901, it applies it to the data buffer 11, reads out the transfer data to which a parity bit has been added, and sends it to the data reception device 2 via the read transfer data bus 904, regardless of the clock a, and also detects an error. Transfer data and parity bits are input to the circuit 14.

This error detection circuit 14 uses parity pits to check the validity of the transferred data, and if the transferred data shows an invalid value due to a buffer failure, it sets the error report 903 to "1" and receives the data. Send to device 2. Note that if the transfer data is a correct value, the error report 903 remains rQJ.

In the data receiving device 2, the transfer data read from the data buffer 11 is set in the transfer data receiving register 25, and at the same time, an error report 9 is sent from the error detection circuit 14.
A value of 03 is set in the error reception port F#124. Then, the error receiving circuit 24 receives the error report 903 as r□,
If , it is determined that the transferred data is normal, and the transferred data is sent to another block, and the next data transfer operation is performed.

On the other hand, error report 903. If it shows "1", a report 202 indicating that an error has occurred is sent to a diagnostic device (not shown). Then, the diagnostic device registers that the data buffer 11 has failed and instructs replacement of the corresponding part.

That is, in this embodiment, a failure in the data buffer 11 can be pointed out by checking the data before transferring it and then transmitting the result of the check together with the data in synchronization with the clock on the receiving side.

Furthermore, it is obvious that if an error detection circuit is added after the transfer data receiving register 25, the output 203 can be checked, and thereby an abnormality in the transfer data receiving register 25 can be detected.

Furthermore, it is clear that if an error detection circuit is provided in parallel with the transfer data reception register 25, an abnormality in the interface can be detected.

Note that in this embodiment, the data is synchronized with the clock on the receiving side and transferred at the same timing, thereby making the data correspond to the error check result of the data. By matching the results of that check, the location of the abnormality can be detected.
For example, if an identifier for each data is added to the check result, correspondence with the data can be established. Furthermore, even if the data comparison check results are transferred with a certain lock delay, the correspondence between the two can still be achieved by subtracting the delay clock.

1. Basics 1. As explained above, the present invention checks the successive data in the buffer in the data transmitting device, and sends the result to the data receiving device together with the transferred data. This has the advantage that when a failure occurs and an error occurs in the transferred data, the diagnostic device can accurately point out the location of the failure.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a data transfer system according to an embodiment of the present invention. Explanation of symbols of main parts 11... Data buffer 14... Error detection circuit 24... Error receiving circuit

Claims (1)

[Claims] (1) A data transfer system comprising a data transmitting device including a storage means for storing a plurality of data to be transferred, and a data receiving device receiving the data, the data transmitting device being provided with It is characterized by comprising an error detecting means for detecting the presence or absence of each error, and a receiving means provided in the data receiving device and receiving the data and the detection result of the error detecting means for the data in correspondence with each other. data transfer system.