JPS6014527A - Nonbreak high-speed signal processing circuit - Google Patents

Abstract

PURPOSE:To obtain a nonbreak signal processing circuit by providing a branching circuit of a high-speed digital pulse train, three or more high-speed signal processing circuits for signal processings of an erroneous pulse train, and a majority logic gate which receives output signals of these circuits to output one output. CONSTITUTION:The third order-group high-speed digital signal in an input terminal S is branched into three by a branching circuit 1-1 and is supplied to high- speed signal processing circuits 2a, 2b, and 2c for the third order-the fourth order group conversion. Oneline components of another third order-group signal are supplied to these processing circuits from two different branching circuits. Outputs of these circuits are inputted to a majority logic gate 3-1 simultaneously. This gate operates the majority of three input pulses; and when the gate judges that two pulses have the same polarity at least, a pulse having this polarity is outputted to an output terminal O. That is, even if one of processing circuits 2a, 2b, and 2c is faulty, the output of the gate 3-1 is not affected. The majority logic gate is operated in 10Gb/s, and a time delay for high-speed pulses of <=10Gb/s is not generated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is applicable to high-speed digital communication systems, such as tertiary group (45 Mb/s for North American systems, 34 Mb/s for CBPT systems).

In order to improve the reliability of 1° large-capacity transmission systems for high-speed signal processing circuits that perform higher-order group conversion (Japanese 32Mb/S) or higher, line transmission signal conversion, etc., it has conventionally been necessary to parallelize high-speed signal processing circuits. There is a method of switching with a protection switch (1974 Research and Practical Application Report, Vol. 23, No. 4, p. 605 "Protection Switch")
. This method detects parity errors, frame synchronization loss, pulse output, or code rule errors in high-speed signal processing circuits, and when an error is detected, protects switches installed in combination at the input and output terminals. This is a method for switching at the same time. FIG. 1 shows an example of such a transmission system, in which one line of tertiary group signals is input from the input terminal S and supplied to the protection switch 5-1. The protection switch 5 switches and supplies the third-order group signal to the high-speed signal processing circuit 2-1 or 2-2. Initially, the signal is switched to the high-speed signal processing circuit 2-1 side, multiplexed with the third-order group signal sent via protection switches (not shown), and quickly converted into a fourth-order group signal. The converted fourth-order group signal is sent to the high-speed signal processing circuit 2-3 via the cable 4. The high-speed signal processing circuit 2-3 converts the received fourth-order group signal into a third-order group signal. On the other hand, the grotchism switch 5-2 first connects the high-speed signal processing circuit 2-3 to the output terminal R, and outputs one line of the tertiary group signal to the output terminal R.
Output to. The high-speed signal processing circuits 2-1 and 2-3 are
Each is equipped with error detection functions such as code parity error and code rule error detection after high-speed signal processing, and when an error is detected, the protection switches 5-1 and 5-2 are switched to standby high-speed signal processing circuits. Switch and connect to 2-2 and 2-4 sides. As shown in Part B, the protection switch automatically switches when an error is detected1゜However, according to the above example, the time required for automatic switching is B, i.
0 to 3 i, 5m5ec The system as a whole between Kaka D and Ko has a drawback that it does not operate normally and is often in a so-called instantaneous interruption state.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of redundant configurations that allow instantaneous interruptions as described above, and to provide a signal processing circuit without instantaneous interruptions.

According to the present invention, three or more high-speed signal processing circuits that perform high-speed digital signal processing, a branch circuit for inputting high-speed digital pulse trains in parallel to each of these high-speed signal processing circuits, and three or more high-speed An uninterrupted high-speed signal processing circuit including a majority logic gate that receives an output digital signal from a signal processing circuit and outputs one output according to majority logic is obtained.

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a block diagram showing an embodiment of the present invention. In the figure, a tertiary group high-speed digital signal inputted from an input terminal S is branched into three branches at a branch circuit 1-1, and three high-speed digital signal processing circuits 2a each perform a tertiary-quartic group conversion.
, 2b and 2C. Each of these high-speed signal processing circuits hog receives a third-order group signal for another line from two other branch circuits (not shown). That is, each high-speed signal processing circuit receives signals for three lines. These high-speed signal processing circuits are the same (or similar) circuits that perform cubic-quaternary conversion high-speed digital signal processing.

The outputs processed by each circuit are the majority logic gate 3-1
input at the same time. When this gate takes a majority vote of the three pulses and determines that at least two pulses are the same, it outputs the pulse of that polarity to the output terminal O. In other words, the gate outputs the pulse of the polarity to the output terminal O. Even if one of them malfunctions or stops, the output of the majority logic gate 3-7 will not be affected. The probability that two circuits fail at the same time is extremely small, so reliability is high. Some majority logic gates that operate at speeds of 100 b/s have already appeared, even in the form of blocks, and there is no time delay for high-speed pulses of 10 Gb/s or less. It operates without interruption.

FIG. 3 shows a high-speed transmission system using the high-speed signal processing circuit shown in FIG. and is branched into 3. High-speed digital signal processing circuit 2 a+2e and 2f are branch circuits 1-2
The fourth-order group digital signals supplied from the fourth-order group digital signal are subjected to third-order group conversion and simultaneously outputted to the majority logic gate 3-2. This majority logic gate 3-2 takes a majority vote of the output pulses from the output line corresponding to each high-speed processing circuit among the three output lines of each of the high-speed processing circuits 2d to 2f, and determines that at least two pulses are the same.2b At this time, a pulse of that polarity is output to the output terminal J, so reliability is increased and a signal can be output to the output terminal R without any request.

Further, details regarding the majority logic logic can be found in, for example, ``Tigital Circuit'' published by Sangyo Toshosha, p. 73.

As described above, according to the present invention, a highly reliable high-speed digital signal processing circuit capable of signal processing without momentary interruption can be obtained, contributing to improved reliability of a digital transmission system and signal transmission without momentary interruption.

In the practical example, 3rd order group - 4th order group transformation or 4th order group - 3
Although three high-speed signal processing circuits that perform next-order group transformation are used, the present invention is not limited to these, and other high-speed signal processing circuits that perform next-order group transformation or low-order group transformation may be used. Furthermore, four or more high-speed signal processing circuits may be used as necessary.

In addition, the digital image signal encoding circuit of, for example, the Fukushimi+7 device is used as the fast image processing circuit, and the encoded image information is supplied to the majority logic gate to generate an output signal according to the majority logic. You can also get it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional high-speed transmission system using a protection switch, i2p+ is a block diagram showing an embodiment of the present invention, and FIG. 3 is a block diagram of a high-speed transmission system according to the present invention. 1-1...Branch circuit, 2"+ 2b+ 2C1
2d+ 2er2f...High speed signal processing circuit, 3
...Majority logic gate, 4...Kefle, 5-1. ．． 5-2... Protection switch, S... Input end, R... Output end. M 18

Claims (1)

[Claims] A branch circuit that branches a high-speed digital pulse train, three or more high-speed signal processing circuits that signal-process the branched high-speed digital pulse train, and receives output digital signals from each of the signal processing circuits and outputs one output according to majority logic. An uninterrupted high-speed signal processing circuit including a majority logic gate.