JPS63226754A - Bus data error detecting system - Google Patents

Abstract

PURPOSE:To execute sure data transmission by comparing data outputted from a transmission part with data transmitted to a bus and adding a bit indicating whether the data from the transmission part are correctly transmitted or not to the final bit of transmission data. CONSTITUTION:Data from plural transmission parts connected to the bus 1 is held in a holding means 3 and is sent to the bus 1 through a gate switch 2 in accordance with a clock generated from a timing signal generating part 6. A comparator 4 compares the data held in the holding means 3 with the data sent to the bus 1 based on the clock 6, detects the existence of an error in accordance with the coincidence or noncoincidence between both the data, and outputs the detected result to an output part 5. The output part 5 adds a bit indicating the existence of a data error to the final bit of transmission data. The receiving side decides the validity/invalidity of data based on the final bit. Thus, sure data transmission can be attained by a simple device.

Description

[Detailed description of the invention] [Table of contents] Overview Industrial field of application Prior art (Figure 4) Problems to be solved by the invention Means for solving the problems (Figure 1) Working examples (Figure 1) (Figures 2 and 3) Effects of the invention [Summary] In a bus-type data transmission system in which a plurality of transmitters are connected to a common bus, it is possible to detect whether or not data to be transmitted is correctly output onto the bus. In addition, the result is sent together with the transmission data as the final bit of the transmission data, so that it is easy to determine whether the data is valid or invalid on the receiving side.

[Industrial application field]

The present invention relates to a bus data error detection method in bus-type data transmission in which data from a plurality of interface units is sent out to a bus and data is transmitted via this bus.

When transmitting data from multiple transmitters to a single receiver, in addition to connecting each transmitter directly to the receiver, the data from each transmitter is connected to a bus, which is a common transmission line. There is a bus-type data transmission system that connects the receiver to the receiver. The latter bus-type data transmission method is widely used because it allows data transmission with a relatively simple configuration when connecting a transmitting section located far away to a receiving section.

However, when one of the transmitters connected to the bus is inserted into or disconnected from the system, it may have an adverse effect on the output data of the other transmitters, so that the data is not correctly sent onto the bus. It is necessary to know whether
There is a need for a method for this purpose.

[Conventional technology]

FIG. 4 shows a conventional example for checking sent data in a bus-type transmission system.

Figure 4 (A) shows the overall system diagram, and Figure 4 (B) shows the overall system diagram.
) shows some details.

In the figure, a plurality of transmitting sections 1, 2, . . . - transmitting section n are connected to a receiving section 41 via a bus 40.

As shown in FIG. 4(B), the transmitting unit 42 has a CRC calculation unit 45, which calculates a CRC error check bit shown as CB in the figure for the transmission data shown as (A) in the figure. The data is exchanged with the data that it has, and sent to the bus 40 via the buffer 43. CRC operation (Check
k Redundancy Code operation) is obtained by performing a predetermined logical operation on data A1, A2, and A3.

That is, for example, a predetermined logical operation is performed using data A1, A2, and A3 to obtain CRCI, and the CRCI is added after these bits CRC1, data A1, A2, and A3. This logical operation is not particularly specified, but is predetermined.

Similarly to data A1, A2, A3, data B1,
A predetermined logical operation is also performed on B2 and B3, and the CRC
Get 2. This CRC2 is inserted after the data B1, B2, and B3, sent out to the bus 40, and transmitted to the receiving section 41 via this bus 40.

In the receiving section 41 , the data (B) is sent to the CRC calculating section 47 via the buffer 46 . CRC calculation section 47
Then, A1, A2, A3, B1, B2 in data [B]
, B3, performs the same logical operation as the CRC operation of the transmitter, and compares it with the CRC error check bit in the received data. As a result, if there is a difference between the two, it means that there was an error, and if there is no difference, it means that there was no error.

[Problem that the invention seeks to solve]

Although it is possible to check whether the data output on the bus is correct using this conventional technology, the problem is that it requires complex processing such as CRC calculation and CRC check pit comparison. have.

In addition, in order to check for errors in each transmitted data, a CRC calculation is required for each transmitted data, and several CRC check bits must be added to the data, which solves the problem of poor transmission efficiency. have

[Means for solving problems]

FIG. 1 is a diagram showing the principle of the invention. In the figure, 1 is a bus, and a large number of transmitters are connected to this bus to transmit data, but in FIG. 1, one transmitter, which will be explained below, is shown. The transmitting section includes a holding means 3 for temporarily holding data to be transmitted, a gate switch 2, a timing signal generating section 6, a comparison circuit 4, and an output section 5.

The data to be transmitted will be transmitted to the bus l via the holding means 3 and the gate switch 2.

At this time, the data from the holding means 3 and the data on the bus 1 are compared to check whether the correct data is being sent onto the bus. When correct data is not sent out, a data error signal (L
When correct data is being sent out, a no data error signal (H level) is output.

Then, this data error presence/absence signal is attached to the end of the data and sent. On the receiving side, the presence or absence of a data error signal is detected to determine whether the data is valid or invalid.

[Effect]

In this way, the data error presence/absence signal can be added as the final bit to each data, so that the receiving side can determine whether the data is valid or invalid without any processing.

〔Example〕

FIG. 2 shows an embodiment of the invention. In the figure, winter is a bus, and a plurality of transmitters are connected to this bus. Although only one transmitter is shown in FIG. 2, normally many transmitters similar to this will be connected.

The transmitter has a D-FF (D flip-flop) 7 and a gate switch 2, and the data to be output is sent to the D-FF 7.
is input to the D terminal of Data is taken out from the Q terminal of the D-FF 7 in synchronization with the clock, and the gate switch 2 is opened by a timing signal from the timing signal generator 6 to send the data onto the bus.

FIGS. 3(i), (11), and (iii) represent this operation. That is, synchronize the data shown in (ii) that you want to output, such as rl O110J, with the clock in (i),
The signal is outputted from the D-FF7, and further outputted to the bus 1 via the gate switch 2, which is opened by the signal at timing (3) shown in (iii).

The NAND gate 9 functions as a comparison circuit that detects whether the output of the D-FF 7 and the data sent to the bus 1 via the gate switch 2 match. Now, N
As shown in FIG. 2, the three inputs of the AND9, ■, ■, and ■, respectively: ■: the output of the D-FF7, ■: the logical value from the timing signal ■, and ■= the data sent to the Babasu, are sent to the inverter 11. When it is inverted, each data becomes as shown in FIG. 3(v). NAND becomes O when all inputs are "1", but it is clear that when the output to bus 1 is correct for input ■, input ■ will always have the opposite value to ■. When the input section from D-FF7 to bus l is operating correctly, the output of NAND9 is always "1", and when there is an error, the output of NAND9 is rOJ.

The D-FF 8 and the gate switch 12 operate as a circuit that receives information indicating the presence or absence of an error from the NAND 9 and adds this information as the final bit to each data.

In Fig. 3 (tilt), when gate switch 2 is opened at timing ■, data ■ (1, 2, 3, 4
,5,) are output to bus 1.

The D-FF 8 receives information from the NAND 9 and outputs it to the gate switch 12 in synchronization with the clock.

The gate switch 12 receives the timing ■ from the timing signal generator 6 and adds the error presence information E from the NAND 9 so that it is exactly the last bit of the data ■.

Similar operations are performed by other transmitters connected to bus 1 (see Figure 3).
This is performed for the data from the second CH shown in viii).

It can be seen that when these data shown in (vj) and (vFs) are integrated on the bus, the data shown in FIG. 3 (ix) is obtained.

As mentioned above, the error presence/absence information E is rlJ (High level) when data is normal and rlJ (High level) when data error is detected.
By selecting OJ (Low level), when a data error is detected, the old gh
level. Note that the error presence/absence information E held by the D-FF 8 as described above is cleared by the clear signal from the timing signal generator 6 by the beginning of the next operation.

〔Effect of the invention〕

As described above, according to the present invention, the presence or absence of errors can be transmitted for each data without performing complicated machine check processing. Data transmission may be enabled.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention, FIG. 2 is an embodiment of the present invention, FIG. 3 is a waveform diagram for explaining the operation, and FIG. 4 is a diagram showing a conventional example. 1-Bus, 2.12-・Gate switch 3...
- Holding means, 4- Comparison circuit, 5- Output section, 6- Timing signal generation section 7, 8-
D-FF. 9- NAND gate, 10.11- Inverter,

Claims (2)

[Claims] (1) In a bus-type data transmission system that transmits data from the transmitter to a bus, a comparing means (4) is provided to compare the data from the transmitter and the data transmitted on the bus, and A bus data error detection method is characterized in that it detects whether or not data has been transmitted correctly. (2) Information indicating whether or not the data from the transmitter has been correctly transmitted is added as the final bit of the transmitted data, and this is transmitted on the bus. Bus data error detection method.