JPS58220546A - Digital data transmitting system - Google Patents

Abstract

PURPOSE:To obtain a transmitting system of additional information, which has a high transmission efficiency, by inverting the polarity of all bits or a specified bit of CRCC to be transmitted, to CRCC of other transmitting block, in a transmitting block into which the head bit of an additional information block is inserted. CONSTITUTION:The inside of a coincidence detecting circuit 8 is constituted as shown in the figure as one example, and when contents of a CRCC operating circuit 6 coincide with contents of a shift register 7, a coincidence output is outputted from a terminal A, and unless all bits do not coincide with each other, that is to say, when the contents of the CRCC operating circuit 6 coincide with those which invert the polarity of the contents of the shift register 7, the coincidence output is outputted from a terminal B. That is to say, unless there is an error in a receiving data, one of outputs A and B of the coincidence detecting output 8 becomes ''1'', and an output of an OR gate 9 to which they are inputted becomes ''1'' and becomes a CRCC checking output.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital data transmission system for additional information that is divided and inserted into a main data block.

1 Conventionally, as shown in Figure 1, block synchronization of additional information blocks inserted into main data blocks has been carried out by inserting a synchronization pattern into the additional information block and detecting this through a pattern detection circuit. ing.

Hereinafter, a conventional synchronization detection method for additional information blocks will be explained with reference to the drawings. In Figure 1, (a) is a configuration diagram of a transmission signal, (b) is a configuration diagram of an additional information signal extracted from (a), and (c) and (d) are additional information block synchronization signal detection using the conventional method. It is a block diagram of a circuit. In the signal configuration diagram, the parts indicated by s and s' are synchronization pattern 1. D.
The portions indicated by D' are data portions of main information and additional information. In FIGS. 1(e) and 1(d), 1 is an additional information extraction circuit.

2 is a synchronization signal detection circuit, 3 is a synchronization pattern detection circuit, 4
5 is a synchronizing signal output gate circuit, and 5 is a synchronizing signal detection window control circuit.

Additional information extraction circuit 1 from the data input terminal in FIG. 1(C)
The signal of the configuration shown in FIG. 1(a) inputted to is divided into the main data output and the additional information signal (FIG. 1(b)).
The additional information block consists of a synchronization signal portion S' and an information data portion D', and is input to the synchronization signal detection circuit 2. A synchronization signal detection circuit detects a synchronization pattern S' inserted at a block break from a signal sequence as shown in FIG. 1(b), and outputs a synchronization signal.

However, the same pattern as the synchronization signal pattern S' may appear in the information data bits, and if such a pattern is detected as a synchronization signal, the additional information data will be separated incorrectly and correct information will not be obtained. The synchronization signal detection circuit 2 is constructed as shown in FIG. 1(d), and a method is adopted in which a pattern identical to a synchronization pattern in the information data is excluded.

When the synchronization pattern detection circuit 3 detects a synchronization pattern,
Its output is input to the synchronization signal output gate circuit 4. On the other hand, synchronization signals are inserted at equal intervals, and the amount of synchronization signals
・: The force is input to the synchronization signal detection window control circuit 5, and the synchronization signal detection window control circuit 5 measures the elapsed time from the output synchronization signal, and closes the synchronization signal output gate around the time when the next synchronization signal arrives. 4, and outputs the output of the synchronization pattern detection circuit 3 to the outside as a synchronization signal output. Therefore, even if a synchronization pattern is detected in the area of information data D', no synchronization signal is output, thereby preventing synchronization errors.

As described above, the conventional additional information block synchronization method requires means for preventing erroneous detection in detecting a synchronization signal, which inevitably leads to an increase in circuit scale. Also, in order to insert a synchronization pattern into the additional information block,
There is a problem of reduced transmission efficiency.

The purpose of the present invention is to eliminate the drawbacks of the prior art described above,
It is an object of the present invention to provide a digital data transmission system for additional information that can detect an additional information block synchronization signal with a small number of circuits and has high transmission efficiency.

In digital data transmission, an error detection code such as CRCC is often added to each transmission block in order to detect code errors that occur during transmission.

Normally, in order to check the CRCC for error detection, a CRCC calculation circuit is used to check the data of the block and the CRCC.
are input one after another, and when all the inputs of CR'CC are completed at 4, the operation is performed depending on whether or not the contents of the calculation register are all ''.

By the way, the CRCC calculation circuit performs the same calculation on both the CRCC generation side and the check side. Therefore, when all data bits except the CRCC bits of a block have been sequentially input to the arithmetic circuit, the CRCC check is performed to check whether the contents of the arithmetic register completely match each pit of the received CRCC. Therefore, for example, if the leading pit of the additional information block is added to the inserted transmission block, and if the polarity of the CRCC pit is inverted and transmitted, the CRCC bit of each transmission block will be removed. Error detection and synchronization of additional information blocks can be performed by inputting the data into the CRCC calculation circuit and checking whether the contents of the calculation register match the received CRCC or the received CRCC with the polarity inverted. Detection is possible at the same time. The same thing can be done by inverting specific bits of the CRCC bits. FIG. 2 shows an embodiment of the present invention, and a detailed explanation of the present invention will be given below with reference to FIG. 2. .

In FIG. 2, 6 is a CRCC calculation circuit, 7 is a shift register, 8 is a coincidence detection circuit, 9 is an OR gate, and 10 is an E
xOR gate 11 is a NOR gate 12 is an AND gate.

One block of digital signal input from the signal input terminal is divided into a data bit part and a CRCC bit part.
Then, the CRCC bit portion is input to the shift register 7. The signal is sent serially, first the data bit, then the C
When the RCC bits are input in order, when all the data bits of one transmission block are input to the CRCC calculation circuit B, the CRCC pit determined from the received data remains in the calculation register and the calculation is stopped. do.

Next, the input received CRCC bits enter the shift register 7, and when all the signals for one transmission block have been input, the coincidence detection circuit 8 transfers the contents remaining in the operation register of the CRCC operation circuit B to the shift register 7. Compare the contents of the received CRCC bits contained in 7. The interior of the coincidence detection circuit 8 is configured as shown in FIG.
If the contents match, a match output is output from the A terminal, and if all the pits do not match, that is, if the contents of the CRCC calculation circuit 6 and the polarity inverted contents of the shift register 7 match, I3 is output. Match output is output from the terminal. Ex◇R
If the inputs of 10 match, the output will be '0 //, and if they do not match, the output will be 11'', so all the outputs of Ex OR10 provided for each bit to be compared will be input. The N9R gate 11 outputs '1' if all bits to be compared match, and outputs '0' if even one bit does not match.
All the outputs of xORlo are input to the AND gate. If all the bits to be compared are different, that is, if all the bits are inverted, it outputs "1", and if even one bit matches, it outputs "1". Output '0''.

Therefore, the CRCC calculated from the received data and the received C
If the RCC matches, or if the inverted polarity of the received CRCC matches, that is, if there is no error in the received data, either the A or B output of the match detection circuit 8 becomes '1'. , etc., the output of the OR gate 9 to which these are input becomes "", which becomes the CRCC check output. On the other hand, if only the transmission block in which the first bit of the additional information block has been inserted is transmitted with the CRCC bit inverted, the B output of the matching circuit 8 will be 11" only when that block is received, so this is added. It is output as an information synchronization signal to synchronize additional information blocks.

According to the present invention, synchronization credit can be obtained with a relatively small circuit configuration without adding synchronization bits to the additional information block, and a digital data transmission system for additional information with high transmission efficiency can be realized.

[Brief explanation of drawings]

Figures 1(a) and 1(b) are diagrams of the signal configuration of the conventional system.
1(c) and (d) are block diagrams of a conventional additional information block synchronization signal detection circuit, FIG. 2 is a block diagram of an embodiment according to the present invention, and FIG. 3 is a specific circuit of the coincidence detection circuit 8. It is a diagram. 6...CRCC calculation circuit 7...Shift register 8...Coincidence detection circuit 9...
・OR gate 10...Ex◇R gate 11...
・NOR Gate 12...AND Gate Agent Patent Attorney Usui 1) 11th Turnip: +! ,' +1. F. one

Claims (1)

[Claims] For each block consisting of a fixed amount of digital data, a transmission block is constructed by dividing and inserting one or several bits of additional information block data, which also consists of a fixed amount other than the main data, to eliminate code errors that occur during transmission. In a data transmission method that adds and transmits a CRCC (cyclic code) for detection, in the transmission block where the first bit of the additional information block is inserted, the polarity of all bits of the CRCC to be transmitted or a specific pit is A digital data transmission method characterized by inversion with respect to other transmission blocks 0CRCC.