JPS6376623A - Crc generating circuit - Google Patents

Crc generating circuit

Info

Publication number
JPS6376623A
JPS6376623A JP22281786A JP22281786A JPS6376623A JP S6376623 A JPS6376623 A JP S6376623A JP 22281786 A JP22281786 A JP 22281786A JP 22281786 A JP22281786 A JP 22281786A JP S6376623 A JPS6376623 A JP S6376623A
Authority
JP
Japan
Prior art keywords
crc
data
inputted
terminal
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22281786A
Other languages
Japanese (ja)
Inventor
Natsuo Fujita
藤田 夏男
Shigemitsu Mizukawa
繁光 水川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP22281786A priority Critical patent/JPS6376623A/en
Publication of JPS6376623A publication Critical patent/JPS6376623A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To attain data transmission with higher quality by preserving the quality of transmitted data and updating CRC data when new data are added to a transmitting data column and a relaying transmission is executed. CONSTITUTION:When new data are added and a CRC generation is executed, the received data inputted from a data input terminal 1 and new data inputted from a new data input terminal 2 are added by an MOD 2 adder 15 and inputted to an MOD 2 adder 13. The data are fed back to a CRC arithmetic part and CRC operation is executed. A gate 14 controls, by the signal inputted from an information/CRC changing-over terminal 4, whether or not the CRC operation is executed. The arithmetic result at the CRC arithmetic part is outputted to a delaying device 10 and the result to add the CRC of the received data and MOD2 with an MOD2 adder 16 is inputted to a selecting device 6. The selecting device 6 changes over the new information inputted from the new data input terminal 2 and the CRC and outputs them to a data output terminal 3, by the input signal of an information/CRC changing-over terminal 4.

Description

【発明の詳細な説明】 〔産業上の利用分野J この発明は、中継時に新たなデータを付加しながらデー
タ伝送を行う場合の誤り検出に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application J This invention relates to error detection when data is transmitted while adding new data during relay.

[従来の技術〕 4s2図は従来のCRC(Cyclic Redund
ancy Checle Code)生成回路を示すブ
ロック図であり、(1)はデータ入力端子、(2)は新
データ入力端子、(3)はデータ出力端子、(4)は情
報/ CRC9J替端子、(5)および(6〕は選択器
、(7)〜(lO)は遅延器、(11)〜(13)はM
OD 2加算器、(14) #fゲート、(17)はデ
ータ付加/無付加切替端子である。
[Prior art] The 4s2 diagram shows the conventional CRC (Cyclic Redundant
(1) is a data input terminal, (2) is a new data input terminal, (3) is a data output terminal, (4) is an information/CRC9J replacement terminal, (5) ) and (6] are selectors, (7) to (lO) are delay devices, (11) to (13) are M
OD 2 adder, (14) #f gate, (17) is a data addition/non-addition switching terminal.

次に動作について説明する。受信データに対して新たな
データを付加するかしないかをデータ付加/無付加切替
端子(17)の入力信号によシ選択器(5)で選択する
。また、CRC主成部は、遅延器(7)〜(10)%M
OD2加算器(11)〜(13)、ゲート(14)およ
び選択器(6)によシ構成され、CRCと演算を行わな
い場合は情報/ CRC切替端子(4)には常に情報を
選択する信号を入力する。付加データにCRC演算を行
う場合は、まず情報/ CRC切替端子(4)に情報を
選択する信号を入れることによシ選択器(6)は新デー
タ入力端子(3)よシ入力された新しいデータをそのま
まデータ出力端子(3)に出力する。その間CRC演算
回路において新しいデータに対してCRC演算を行い、
情報出力後情報/CRC(71I替端子(4)にCRC
を選択する信号を入れることにより、CRC演算結果を
データ出力端子(3)に出力する。
Next, the operation will be explained. Whether or not to add new data to the received data is selected by the selector (5) depending on the input signal of the data addition/non-addition switching terminal (17). In addition, the CRC main component includes delay devices (7) to (10)%M
Consists of OD2 adders (11) to (13), gates (14), and selectors (6), and always selects information at the information/CRC switching terminal (4) when no CRC calculation is performed. Input the signal. When performing a CRC calculation on additional data, first input a signal for selecting information to the information/CRC switching terminal (4), and then the selector (6) selects the new data input from the new data input terminal (3). The data is output as is to the data output terminal (3). During that time, the CRC calculation circuit performs CRC calculation on the new data.
After information output information/CRC (CRC on 71I replacement terminal (4)
By inputting a signal for selecting , the CRC calculation result is output to the data output terminal (3).

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来のCRC演算回路は以上のように構成されているの
で、データ伝送において中継時に新たなデータを付加す
ると、新しいデータに対してCRC演算を行い、中継器
の受信データにCRCエラーが発生してもそのことを伝
送することができないという問題があった。
Conventional CRC calculation circuits are configured as described above, so when new data is added during relay in data transmission, a CRC calculation is performed on the new data and a CRC error occurs in the data received by the repeater. However, there was a problem in that it was not possible to transmit this information.

この発明は上記のような問題点を解消するためになされ
たもので、データ伝送において中継伝送する場合、中継
後の受信データに対してCRCチェックを行うことによ
り、中継前のデータに対するCRCチェックも同時に行
うことができるCRC演算回路を得ることを目的とする
This invention was made to solve the above-mentioned problems, and when relaying data transmission, by performing a CRC check on the received data after the relay, it is also possible to perform a CRC check on the data before the relay. The object of the present invention is to obtain a CRC calculation circuit that can perform simultaneous operations.

〔問題点を解決するための手段J この発明に係るCRC生成回路は、データ伝送において
、中継時にデータを付加する場合、中継器の受信データ
と新しいデータをMOD2で加算したデータに対してC
RC生成を行い、さらに受信データに対するCRCをM
OD2で加算したものを中継器出力のCRCとして、送
信データに付加したものである。
[Means for Solving Problems J] In data transmission, when data is added during relay, the CRC generation circuit according to the present invention generates a C
Generates RC, and also generates CRC for received data.
The value added at OD2 is added to the transmitted data as the CRC of the repeater output.

〔作用〕[Effect]

この発明におけるCRC生成回路は、中継器の受信デー
タと新たなデータをMOD2で加算したものに対してC
RC生成を行うので、中継データを受信した時に、中継
後のデータに対する誤りだけでなく、中継器受信データ
の誤りもそのまま保存されているため、CRCチェック
により中継前後の誤りを検出できる。
The CRC generation circuit in this invention performs a C
Since RC generation is performed, when relay data is received, not only errors in the data after relay but also errors in the data received by the repeater are saved as they are, so errors before and after relay can be detected by a CRC check.

〔実施例J 以下、この発明の一実施例を図について説明する。第1
図において%(1)はデータ入力端子であり、中継器の
受信データが入力される。(2)は新データ入力端子で
あシ、中継後に送信する情報が入力される。(5)は選
択器であり、データ付加/無付加切替端子(17)の切
替により、受信データに新たなデータを付加するかどう
かを選択する。(7)〜(10)は遅延器、(11)〜
(13)はMOD2加算器、(14)はゲート、(15
)および(16)はMOD2加算器で(7)〜(16)
によりCRC生成部を構成する。捷た(6)は選択器で
あり、情報/CRC4y′J替端子(4)に入端子る信
号の9J替により、データ出力端子(3)から出力され
るデータの情報/ CRC切替を行う。
[Embodiment J Hereinafter, one embodiment of the present invention will be described with reference to the drawings. 1st
In the figure, %(1) is a data input terminal, into which data received by the repeater is input. (2) is a new data input terminal, into which information to be transmitted after relaying is input. (5) is a selector which selects whether or not to add new data to the received data by switching the data addition/non-addition switching terminal (17). (7) to (10) are delay devices, (11) to
(13) is a MOD2 adder, (14) is a gate, (15
) and (16) are MOD2 adders (7) to (16)
The CRC generation section is configured by: Switch (6) is a selector, which performs information/CRC switching of data output from the data output terminal (3) by switching 9J of the signal input to the information/CRC4y'J switching terminal (4).

次に動作について説明する。受信データに対して新たな
データを付加するかしないかをデータ付加/無付加切替
端子(17)の入力信号により選択器(5)で選択する
。データ出力端子(3)から情報を出力するかCRCを
出力するかは情報/ CRC切替端子(4)の入力信号
により選択器(6)が行なう。CRC生成を行わない場
合は常に情報を選択する。
Next, the operation will be explained. Whether or not to add new data to the received data is selected by the selector (5) based on the input signal of the data addition/non-addition switching terminal (17). A selector (6) determines whether information or CRC is output from the data output terminal (3) based on the input signal of the information/CRC switching terminal (4). If CRC generation is not performed, always select information.

新たなデータを付加し、CRC生成を行う場合は、デー
タ入力端子(1)から入力された受信データと新データ
入力端子(2)から入力された新しいデータをMOD2
加算器(15)により加算し、MOD2加算器(13)
に入力する。そのデータは遅延器(7)〜(10)、M
OD2加算器(11)、(12)で構成されるCRC演
算部に帰還され、CRC演算される。ゲー) (14)
I/iCRC演算を行うかどうかの制御を行うもので、
情報/ CRC切替端子(4)から入力された信号によ
り制御する。CRC演算部での演算結果は遅延器(lO
)に出力され、さらにMOD2加算器(16)により受
信データのCRCとMOD2加算したものを選択器(6
〕に入力する。選択器(6)は情報/CRC切替端子(
4)の入力信号により、新データ入力端子(2)から入
力された新しい情報とCRCを切り替えてデータ出力端
子(3)に出力する。
When adding new data and generating a CRC, MOD2 converts the received data input from the data input terminal (1) and the new data input from the new data input terminal (2).
Add by adder (15), MOD2 adder (13)
Enter. The data is transmitted to delay devices (7) to (10), M
The signal is fed back to the CRC calculation unit composed of OD2 adders (11) and (12), and subjected to CRC calculation. Game) (14)
This controls whether or not to perform I/iCRC calculations.
It is controlled by the signal input from the information/CRC switching terminal (4). The calculation result in the CRC calculation section is sent to a delay device (lO
), and the MOD2 adder (16) adds the received data CRC and MOD2 to the selector (6).
]. The selector (6) is the information/CRC switching terminal (
In response to the input signal 4), the new information inputted from the new data input terminal (2) and the CRC are switched and outputted to the data output terminal (3).

この回路では、新しいデータと受信データをMOD2加
算したものにCRC演算を施し、さらに受信データのC
RCt−MOD2加算して生成したものを送信データの
CRCとしているため、新しいデータにCRC演算を行
ってCRCを付加したものに、受信データの誤りがさら
に付加され、中継器から出た信号を受信し、CRCチェ
ックすると、中継される前のデータの誤りも検出できる
This circuit performs a CRC operation on the new data and received data added MOD2, and then performs a CRC operation on the received data.
Since the CRC of the transmitted data is generated by adding RCt-MOD2, errors in the received data are added to the new data by performing CRC calculation and CRC, and the signal output from the repeater is not received. However, by checking the CRC, it is possible to detect errors in the data before it is relayed.

〔発明の効果] 以上のように、この発明によればMOD2加算器、遅延
器、ゲート、選択器により、データ中継前のCRCエラ
ーを保存できるように構成したので、従来の回路にわず
かな回路を付加するだけで、より品質の高いデータ伝送
を行うことができる。
[Effects of the Invention] As described above, according to the present invention, the MOD2 adder, delay device, gate, and selector are configured so that the CRC error before data relay can be stored, so that a small amount of circuitry is required in addition to the conventional circuit. By simply adding , higher quality data transmission can be achieved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例によるCRC生成回路を示
すブロック図、第2図は従来のCRC生成回路を示すブ
ロック図である。 図において、(1) #:Il’データ入力端子、(2
)は新データ入力端子、(3)はデータ出力端子、(4
)は情報/CRC切替端子、(5)および(6)は選択
器、(7)〜(10)は遅延器、(11) 〜(13)
RM OD 2加算器、(14)はゲート、(15)お
よび(16)はMOD2加算器、(17) //′iデ
ータ付加/無付加切替端子である。 なお、図中、同一符号は同一、又は相当部分を示す。
FIG. 1 is a block diagram showing a CRC generation circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional CRC generation circuit. In the figure, (1) #: Il' data input terminal, (2
) is the new data input terminal, (3) is the data output terminal, (4
) are information/CRC switching terminals, (5) and (6) are selectors, (7) to (10) are delay devices, (11) to (13)
RM OD 2 adder, (14) is a gate, (15) and (16) are MOD 2 adders, (17) //'i data addition/non-addition switching terminal. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

【特許請求の範囲】[Claims] 伝送データ列に新たなデータを加えて中継伝送する時に
、伝送されたデータの品質を保存しつつCRCデータを
更新することを特徴とするCRC生成回路。
A CRC generation circuit that updates CRC data while preserving the quality of the transmitted data when adding new data to a transmission data string and relaying it.
JP22281786A 1986-09-19 1986-09-19 Crc generating circuit Pending JPS6376623A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22281786A JPS6376623A (en) 1986-09-19 1986-09-19 Crc generating circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22281786A JPS6376623A (en) 1986-09-19 1986-09-19 Crc generating circuit

Publications (1)

Publication Number Publication Date
JPS6376623A true JPS6376623A (en) 1988-04-06

Family

ID=16788374

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22281786A Pending JPS6376623A (en) 1986-09-19 1986-09-19 Crc generating circuit

Country Status (1)

Country Link
JP (1) JPS6376623A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220546A (en) * 1982-06-16 1983-12-22 Hitachi Ltd Digital data transmitting system
JPS58220545A (en) * 1982-06-16 1983-12-22 Hitachi Ltd Digital transmitting system
JPS61245727A (en) * 1985-04-24 1986-11-01 Canon Inc Data transmitting method
JPS6229239A (en) * 1985-07-30 1987-02-07 Toshiba Corp Frame synchronizing system in cyclic information transmitter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58220546A (en) * 1982-06-16 1983-12-22 Hitachi Ltd Digital data transmitting system
JPS58220545A (en) * 1982-06-16 1983-12-22 Hitachi Ltd Digital transmitting system
JPS61245727A (en) * 1985-04-24 1986-11-01 Canon Inc Data transmitting method
JPS6229239A (en) * 1985-07-30 1987-02-07 Toshiba Corp Frame synchronizing system in cyclic information transmitter

Similar Documents

Publication Publication Date Title
JPS6376623A (en) Crc generating circuit
US20050066258A1 (en) Error decoding circuit, data bus control method and data bus system
JPH0221180B2 (en)
WO2006106576A1 (en) Parity prediction circuit and logic operation circuit using the same
JP3497691B2 (en) Transmitter / receiver circuit
JPS612440A (en) Parallel data transmitter
JPH02249332A (en) Redundancy system selection circuit
KR100234703B1 (en) Data fault checking method
JP2000207425A (en) Calculation method and device for power consumption
JPH11150460A (en) Selection method and selector
JPH02264337A (en) Data transfer control system
JPH0362738A (en) Arithmetic device
JPH0474234A (en) Simulation method for semiconductor integrated circuit
JPH06132938A (en) Frame conversion error correcting circuit
JPS63248241A (en) Communication equipment for adaptive data delayed in network
JPH05300199A (en) Serial data transfer equipment
JPS633342B2 (en)
JPH0619730A (en) Automatic switch check system for parity
JPH06311141A (en) Crc error detection circuit
JPS6095631A (en) Operating system
JPS62281628A (en) Data communication equipment
JPH09282144A (en) Asynchronous 1-bit adder and asynchronous full adder
JPS63153800A (en) Check circuit for information on inside of rom
JPH0685714A (en) Line switching method
JPH03104320A (en) Decoder for burst error correction code