JPS6095631A - Operating system - Google Patents

Operating system

Info

Publication number
JPS6095631A
JPS6095631A JP20380683A JP20380683A JPS6095631A JP S6095631 A JPS6095631 A JP S6095631A JP 20380683 A JP20380683 A JP 20380683A JP 20380683 A JP20380683 A JP 20380683A JP S6095631 A JPS6095631 A JP S6095631A
Authority
JP
Japan
Prior art keywords
carry
adder
signal line
circuit
adding circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20380683A
Other languages
Japanese (ja)
Inventor
Takahiko Sakai
酒井　高彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP20380683A priority Critical patent/JPS6095631A/en
Publication of JPS6095631A publication Critical patent/JPS6095631A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G06F7/508—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages using carry look-ahead circuits

Abstract

PURPOSE:To make a processing speed of an adder variable, and to increase a processing speed in case there is no carry, by deciding in advance whether a carry of an adding circuit exists or not, and controlling a carry propagation. CONSTITUTION:A numerical value to be added is inputted to adding circuits 21, 22 and 23 through signal lines 111, 112. Whether a carry is generated in the adding circuits 21, 22 or not is decided in advance, and ''0'' and ''1'' are outputted to a signal line 26, in case no carry is generated, and in case a carry is generated, respectively. In case of ''0'', an output of AND gates 24, 25 is ''0'' and a signal line 241 being a carry input of the adding circuit 22 is determined to ''0'' irrespective of an operation result of the adding circuit 21. On the other hand, in case of a carry, the signal line 26 becomes ''1'', therefore, a carry determined by an operation result of the adding circuit 21 is propagated to the AND gate 24. In the same way, a carry of the adding circuit 22 is propagated to the adding circuit 23 through the AND gate 25 and a signal line 251.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はｍピット加算回路を１個使用してｎビット加算
器として使用される加算器に用いて好適な演算方式に関
する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an arithmetic method suitable for use in an adder that uses one m-pit adder circuit and is used as an n-bit adder.

〔発明の技術的背景とその間電点〕[Technical background of the invention and electric point between them]

第１図は、ｎビットの加算器をｍビット加算回路３１固
でｋｔａしたときのブロック図を示したものである。（
ｎ−３ｍ）この例において、加算回路１ノにより生じる
桁上り（キャリー）は信号ライン１１１により瞬接する
上位の加算回路１２へ供給され、又、この加η４回路１
２により生じる桁上りは信号線１１２を介して次段の加
算回路１３に供給される。これら桁上げは、各加算回路
１１・１２・１３にて順次演□□□−を必要とし、これ
らが加算器の最大遅延経路となっていた。FIG. 1 shows a block diagram when an n-bit adder is ktaed by an m-bit adder circuit 31. In FIG. (
n-3m) In this example, the carry generated by the adder circuit 1 is supplied to the upper adder circuit 12 which is momentarily connected via the signal line 111, and this adder η4 circuit 1
The carry generated by 2 is supplied to the adder circuit 13 at the next stage via the signal line 112. These carries require sequential operations □□□- in each of the adder circuits 11, 12, and 13, and these constitute the maximum delay path of the adder.

図において、桁上りか生じない場合の信号線１１１・１
１２の状態は０″となっている。In the figure, signal line 111.1 when only carry occurs
The state of 12 is 0''.

信号線１０１・１０２へ供給される数値（加算すべき値
）が、加九回路１ノ・１２によって加算された結果、桁
上りか生じない場合の遅延を考えたとき、初期状態で信
号線１１１・１１２を伝播する信号が”１”となってい
たとすれば、まず、加算回路１２はこの信号線１１ノの
状態が決定してから鼠算全開始することになり、その演
３ｖ！、結果により信号線１１２の状態が“０”となる
。つまり、各加ｈ１路１ノ・１２から桁上げが生じない
一合であっても、ＡｉＪ段に位置する加算回路１１の状
態に従かい各加算回路１２・１３にて桁上げのために順
次演算全必要とする。このため、桁上げの経路が常に最
大遅延経路となっていた。Considering the delay when only a carry occurs as a result of the addition of the numerical values (values to be added) supplied to the signal lines 101 and 102 by the adder circuits 1 and 12, the signal line 111 in the initial state - If the signal propagating through signal line 112 is "1", first, the adder circuit 12 starts the calculation after the state of signal line 11 is determined, and the operation 3v! As a result, the state of the signal line 112 becomes "0". In other words, even if a carry does not occur from each add h1 path 1-12, the adder circuits 12 and 13 follow the state of the adder circuit 11 located in the AiJ stage and are sequentially processed for carry. All calculations are required. For this reason, the carry path was always the path with the largest delay.

ところ、で、桁上げは常に生じるものではなく、加算さ
れる数値の内容により、あらかじめ桁上げが生じないと
判断できる場合もある。桁上げが生じない場合の遅延時
間は、各加算回路１１・１２・１３による動作遅延だけ
で済むはずである。従って、この加算器に入力される数
値の内容が予め予測小米、その結果、桁上げの有無全判
断できる場合は、加算器の処理速度を桁上げの有無によ
り”Ｊ変とすることができるはずである。However, carry does not always occur, and depending on the contents of the numerical value to be added, it may be determined in advance that carry will not occur. In the case where no carry occurs, the delay time should be only the operation delay caused by each of the adder circuits 11, 12, and 13. Therefore, if the content of the numerical value input to this adder is predicted in advance, and as a result, it is possible to determine whether there will be a carry or not, the processing speed of the adder should be able to be changed to "J" depending on the presence or absence of a carry. It is.

〔発明の目的〕[Purpose of the invention]

本発明は上記事情に基づいてなされたものであり、桁上
げ伝播を制御することにより、処理速度′？ｒ：司変と
する成算方式を提供することを目的とする。The present invention has been made based on the above circumstances, and by controlling carry propagation, processing speed '? r: The purpose is to provide a method for achieving success.

〔発明の楓要〕[Keystone of invention]

本発明は上記目的を実現するため、ｎビット加勢、器を
ｍビット加算回路６個で栴瓜するものにおいて、桁上り
は常に生じるものではなく、加算される数値内容により
判断できる場合もあること全利用して、各加算回路間に
存在する桁上り伝播路にアンドゲートを挿入し、このア
ンドゲートは前段（下位）に位飯する加＞１回路より出
力される桁上り信号と、外部より各アンドゲートに対し
共通に与えられる桁上り有無の判断信号とを入力とし、
この信号（判断信号）Ｋより桁上げ伝播をコントロール
するセ４成としたものである。In order to achieve the above-mentioned object, the present invention provides that, in a device in which an n-bit addition circuit is combined with six m-bit addition circuits, carry does not always occur, but can sometimes be determined based on the contents of the numerical values to be added. An AND gate is inserted into the carry propagation path that exists between each adder circuit, and this AND gate connects the carry signal output from the previous (lower) stage (lower) circuit and the carry signal from the outside. Inputs a carry-presence judgment signal commonly given to each AND gate,
This signal (judgment signal) K is used to control carry propagation.

このことにより加算器の処理速度を桁上げの有無により
再認とし、桁上りが無い場合の加）；処理を高速化する
ことができる。As a result, the processing speed of the adder can be checked depending on the presence or absence of a carry, and the processing speed can be increased when there is no carry.

〔発明の実施例〕[Embodiments of the invention]

以下、第２図を使用して本発明実施例につき詳述する。 Hereinafter, embodiments of the present invention will be described in detail using FIG.

８８２図は本発明が実現される加算器を示す実施例であ
る。図において２ノ・２２・２３はｎビットの加算器を
朽戟するｍビット栴成の各加算器回路である。第１図に
示した例との差異は、加算回路２１・２２・２３の間に
アンドゲート２４・２５が挿入されている点にある。ア
ンドゲート２４・２５の一入力端子には外部より信号線
２６を介し桁上り有無の信号が共通に与えられている。FIG. 882 is an embodiment showing an adder in which the present invention is implemented. In the figure, numerals 2, 22, and 23 are m-bit adder circuits that replace the n-bit adder. The difference from the example shown in FIG. 1 is that AND gates 24 and 25 are inserted between adder circuits 21, 22, and 23. A signal indicating the presence or absence of carry is commonly applied to one input terminal of the AND gates 24 and 25 from the outside via a signal line 26.

アンドゲート２４の他方の入力端子には加算回路２１の
桁上り出力が信号ｌＮ１２１’ｌ：介して、又、アンド
ゲート２５の他方の入力端子には加算回路２２の桁上り
出力が信号線１２２を介して供給されている。アンドゲ
ート２４・２５は両入力の論理積金とって次段の加算回
路における桁上り入力端子（ＣＩ）へ供給される。The carry output of the adder 21 is sent to the other input terminal of the AND gate 24 via the signal lN121'l:, and the carry output of the adder 22 is sent to the other input terminal of the AND gate 25 via the signal line 122. Supplied via. AND gates 24 and 25 take the logical product of both inputs and supply it to the carry input terminal (CI) of the next stage adder circuit.

以下、本発明の動作につき詳述する。The operation of the present invention will be explained in detail below.

まず、信号？ｔＭ１１１・１１２を介し、加算回路２１
・２２・２３に加算すべき数値が入力される。これら数
値内容により、加算回路２ノ・２２で桁上げを生じるか
否かが予め判断（ＣＰＵファームウェア）され、桁上げ
が生じない場合は”０″、桁上げを生じる可能性がある
場合は“１″か信号線２６に対し出力される。桁上げが
生じない場合、信号線２６の状態は０”であるため、ア
ンドゲート２４・２５出力は６０″である。部ち、加算
回路２２の桁上り入力である信号線２４ノの状態は、加
算回路２１の演算結果によることなく、信号線２６の状
１ルが０”となることにより０″に決定される。加賀４
回路２３の桁上り入力である信”ｉｌＭ　２５１も同様
である。First, the signal? Addition circuit 21 via tM111 and tM112
- The numerical value to be added to 22 and 23 is input. Based on the content of these numerical values, it is determined in advance (CPU firmware) whether or not a carry will occur in the adder circuits 2 and 22. If a carry will not occur, it will be "0", and if there is a possibility that a carry will occur, it will be "0". 1'' is output to the signal line 26. When no carry occurs, the state of the signal line 26 is 0'', so the outputs of the AND gates 24 and 25 are 60''. The state of the signal line 24, which is the carry input of the adder circuit 22, is determined to be 0'' when the state of the signal line 26 becomes 0'', regardless of the calculation result of the adder circuit 21. . Kaga 4
The same goes for the signal ilM 251 which is the carry input of the circuit 23.

一方、桁上げを生じる可能性がある場合、信号＆！２６
の状態は６１″となるため、アンドゲート２４（信号線
２４））には、加り０回路２ノの演算結果により決定さ
れる桁上げが伝播する。On the other hand, if there is a possibility of causing a carry, signal &! 26
Since the state of is 61'', the carry determined by the calculation result of the addition 0 circuit 2 is propagated to the AND gate 24 (signal line 24).

つまり、桁上げの可能性がある場合には、加算回路２ノ
で生じる桁上けが加ν２回路２２へ伝ゴーする。同様に
、加算回路２２の桁上げは、アンドゲート２５、信号＆
１２５１を通じて加算回路２３へ伝播する。同様に、加
算−に８６２２の桁上げは、アンドゲート２５、イー号
に２５１に通じて加算回路２３へ伝播する。That is, if there is a possibility of a carry, the carry generated in the adder circuit 2 is transmitted to the adder v2 circuit 22. Similarly, the carry of the adder circuit 22 is carried out by the AND gate 25 and the signal &
1251 to the adder circuit 23. Similarly, the carry of 8622 to the addition - is propagated to the addition circuit 23 through the AND gate 25 and the E number 251.

〔発明の効果〕〔Effect of the invention〕

以上説明の如く本発明によれば桁上げのない加算を行な
う場合、信号線２４ノ・２５１の状態は信号線２６を伝
播する信号により固定されてしまう。従って加算器の出
力は、各加算回路の遅延時間のみを考えるだけで良い。As described above, according to the present invention, when addition without carry is performed, the states of the signal lines 24 and 251 are fixed by the signal propagated through the signal line 26. Therefore, for the output of the adder, it is only necessary to consider the delay time of each adder circuit.

これにより、あらかじめ加算回路の桁上げの有無を判断
できる場合には、加算器の処理速度を可変とすることが
出来、桁上げがない場合の処理速度を向上させることが
できる。As a result, if the presence or absence of a carry in the adder circuit can be determined in advance, the processing speed of the adder can be made variable, and the processing speed when there is no carry can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の加算器の構成例を示す図、第２図は本発
明の演算方式が採用される加算器の実施例を示す図であ
る。 ２ノ・２２・２３・・・加算回路、２４・２５・・・ア
ンドゲート。FIG. 1 is a diagram showing an example of the configuration of a conventional adder, and FIG. 2 is a diagram showing an embodiment of an adder in which the calculation method of the present invention is adopted. 2 no.22.23...Addition circuit, 24.25...And gate.

Claims (1)

【特許請求の範囲】[Claims] ｍビットの加算回路をｊ個使用することにより、ｎビッ
ト加算器として使用する加算回路において、下位加算回
路から得られる桁上り出力を、外部から各加算回路共通
に供給される桁上り有無の判断信号に基づきゲートシ、
順次隣接する上位加算回路へ供給することを４Ｂａとす
る演算方式。By using j m-bit adder circuits, in the adder circuit used as an n-bit adder, the carry output obtained from the lower adder circuit can be used to determine the presence or absence of a carry that is commonly supplied to each adder circuit from the outside. gates based on the signal,
An arithmetic method in which 4Ba is sequentially supplied to adjacent upper adder circuits.
JP20380683A 1983-10-31 1983-10-31 Operating system Pending JPS6095631A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20380683A JPS6095631A (en) 1983-10-31 1983-10-31 Operating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20380683A JPS6095631A (en) 1983-10-31 1983-10-31 Operating system

Publications (1)

Publication Number Publication Date
JPS6095631A true JPS6095631A (en) 1985-05-29

Family

ID=16480033

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20380683A Pending JPS6095631A (en) 1983-10-31 1983-10-31 Operating system

Country Status (1)

Country Link
JP (1) JPS6095631A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047975A (en) * 1987-11-16 1991-09-10 Intel Corporation Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5047975A (en) * 1987-11-16 1991-09-10 Intel Corporation Dual mode adder circuitry with overflow detection and substitution enabled for a particular mode

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