JPH0367327A - Addition circuit - Google Patents

Abstract

PURPOSE:To shorten the carry transmitting time by producing the control signals corresponding to the bits of an input pair and controlling the transmission of the carry to a rank higher by two bit via a single gate circuit. CONSTITUTION:The lower rank bits A1 and B1 and the higher rank bits A2 and B2 of the 2-bit input pairs 101 and 102 are inputted to a logic circuit 107. Thus a carry transmission control signal 108 is produced together with a carry generation control signal 109. Both signals 108 and 109 are inputted to a logic circuit 110 as the control signals. Then a carry input Cin is outputted to the output 105 as long as the logical value of the signal 108 is equal to 1. Meanwhile the logical value is outputted to the output 105 when the logical value of the signal 109 is equal to 1. Otherwise the logical value 0 is outputted to the output 105. An arithmetic part 106 adds the binary numbers of 2 bits given to the pairs 101 and 102 to the input Cin and outputs the sums S1 and S2 to an output pair 104. Thus the carry can be transmitted to a rank higher by two bits under the control of a single gate circuit. Then the carry transmitting time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a digital adder circuit, and particularly to a CPA (Ca
rry Propagate Adder: relates to an adder circuit used in an adder that propagates a carry.

[Conventional technology]

The digital adder circuit can realize the logic shown in Table 13.
It is composed of a logic circuit called a full adder with two inputs and two outputs.

Table 1 In the arithmetic logic of the full adder, there is no reason to distinguish any particular input from the others among its three inputs. However, when using a full adder in a CPA, one of the three inputs is designated as a carry-only input to distinguish it from the others, and the carry propagation time is minimized by minimizing the circuit that serves as the signal propagation path from the carry input to the carry output. Improvements have been made to shorten the time. However, the carry propagation path requires at least one gate circuit for each bit adder circuit. FIG. 5 is a diagram showing an example of CPA using a conventional static type adder circuit, and FIG. 6 is a diagram showing an example of CPA using a conventional dynamic type adder circuit.

[Problem to be solved by the invention]

The conventional adder circuit described above requires at least one gate circuit in the carry propagation path of each full adder, so in adders that handle numbers with long bit lengths, the carry propagation time becomes long, resulting in a slow calculation speed. The disadvantage was that it was slow.

As a countermeasure for this, CLA (11: early Look
Ahead: carry ahead), but since the CLA circuit itself has signal delays, it is difficult to satisfy the required calculation speed even when using GLA, especially when performing calculations with a long bit length. is often difficult. Therefore, it is required to further shorten the carry propagation time of each full adder.

An object of the present invention is to provide an adder circuit in which the carry propagation time is shorter than in the past.

[Means to solve the problem]

The adder circuit of the present invention has a first input pair of 2 bits, a second input pair of 2 bits, a third input input of a carry, and a 2 bit pair. The first pair of outputs that output carry, the second output that outputs the carry, the first pair of inputs, the second pair of inputs, and the binary values given to the third input are added, and the sum is added to the first pair of outputs. an arithmetic unit that outputs an output pair to an output pair; and a logical value of the lower bit of the first input pair and the lower bit of the second input pair are not equal to each other, and the upper bit of the first input pair and the second input pair are a function of detecting that the logical values of the upper bits of are not equal to each other and outputting that information, and that the logical values of the lower bits of the first input pair and the lower bits of the second input pair are both 1; and the logic value of at least one of the upper bits of the first input pair and the upper bits of the second input pair is 1, or regardless of the state of the lower bits, the upper bits of the first input pair detecting that the logical values of the upper bits of the second input pair are both 1;
a first logic circuit having a function of outputting the information; and a first logic circuit that outputs a logic value 1 to the second output or outputs a logic value O to the second output depending on the output of the first logic circuit. , and a second logic circuit having a function of controlling whether or not the logic value of the third input is propagated to the second output.

[Effect]

Since the carry propagation to the upper 2 bits is controlled by one gate circuit, the carry propagation time is shortened.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an adder circuit according to an embodiment of the present invention.

Lower bit A1 and upper bit A2 of 2-bit input pair 101 and lower bit B1 of 2-bit input pair 102
and upper bit B2 are input to a first logic circuit 107, which generates a carry propagation control signal 108 and a carry generation control signal 109. Carry propagation control signal 1
08 is obtained by (AIΦB,) (A2■n2), and the carry generation control signal 109 is obtained by A,.B1.(A2+82) + (A2.B2). Here, the symbol ■ means exclusive OR, . means logical AND, and + means logical OR operation.

The second logic circuit 110 inputs the signals 10B and 109 as control signals, and when the logic value of the signal tOa is 1, it outputs the carry input C1n input from the input 103 to the output 105 as a carry output Cout. do.

Further, when the logical value of the signal 109 is 1, the input 103
A logic value of 1 is output to output 105 regardless of the state of .

Otherwise, a logic value O is output at output 105. The arithmetic unit 1θ6 adds the 2-bit binary number given to the input pair 101, the 2-bit binary number given to the input pair 102, and the carry input given to the input 103, and obtains the sum Sl and B2 is output to output pair 104.

Note that there is no restriction as to whether the logic of all the signals described here is positive logic or negative logic.

FIG. 2 is a circuit diagram of an embodiment in which the present invention is applied to a static type adder circuit.

Both 201 and 202 are adder circuits of the present invention.

Adder circuit 201 has input 203 and carry input 20
4 given numbers A,, B,, A2. B2.
Add Gin and output the sum S,, S,20
This is an adder circuit that outputs to 5. 207 is a carry propagation control signal, 208 is a carry generation control signal, and 206
Generates a negative logic carry output. Addition circuit 202 receives input A3. B3. A4. B4 and carry input 2
This is a circuit that performs the addition of 06, and the carry propagation control signal 20
9, it is the same as the adder circuit 201 except that the logic of the carry generation control signal 210 and the carry propagation path is reversed.

FIG. 3 is a circuit diagram of an embodiment in which the present invention is applied to a dynamic adder circuit.

301 and 302 are input AI, A2. Bl, B2.
303 is a negative logic carry input Gin, and the addition result S
t, B2 is output to output 304. 306 is a carry propagation control signal, 307 is a carry generation control signal, and negative logic carry Cout is outputted to 305.

308 is a dynamic circuit precharge control signal C.
LK2 is input, and an operation is executed by a clock signal CLKI input from 309.

When a CLA is used in conjunction with this circuit, the number of elements can be reduced by inputting the carry propagation control signal 306 to the GLA circuit.

Note that the adder circuit described here controls carry propagation to the upper 2 bits using one gate circuit, but similarly, carry propagation for 3 bits or more is controlled using one gate circuit. It is easy to extend the present invention to a system controlled by a circuit.

FIG. 4 is a block diagram of an embodiment of an adder circuit using a method in which carry propagation to the upper 3 bits is controlled by one gate circuit.

This adder circuit has a 3-bit input pair 401 (A+, A
2°A3), 402 (B+, B2+ 83), and the carry input are added in the calculation unit 406, and the addition result 404 (
S+, B2. B3), and the carry control signal generator 407 outputs the carry propagation control signal 408.
and the carry generation control signal 409 to the carry control unit 410.
carry control unit 4]0 to carry output 40.
5 is output. Carry propagation control signal 408
is (AIOB+) (A2■[+2) (A
3Φ83), and the carry generation control signal 40
9 is A1・B1・(A2 +82) (A3+8
3) Obtained by +A2・B2 (A3+83) 10A3・B3.

〔Effect of the invention〕

As described above, the present invention has the effect of shortening the carry propagation time by controlling the carry propagation to the upper 2 bits with one gate circuit.

[Brief explanation of drawings]

Fig. 1 is a plot diagram of an embodiment of the adder circuit of the present invention, Fig. 2 is a circuit diagram of an embodiment in which the present invention is applied to a static adder circuit, and Fig. 3 is a plot diagram of an embodiment of the adder circuit of the present invention. FIG. 4 is a circuit diagram of an embodiment of an adder circuit applied to an adder circuit. Figure 'fJ6 is a circuit diagram of an example of a conventional static type adder circuit. FIG. 101.102...2-bit input pair 103...
... Carry input 104 ... 2-bit output pair 105 ...
. . . Carry output 106 . . . Arithmetic unit + (17 . . . Carry propagation control signal 109・
...Carry generation control signal 110...
Second logic circuits 201, 202 for controlling carry...
-Addition circuit 203...Input 204...Carry input 205...Output 207.209...Carry propagation control signal 208.2
10...Carry generation control signal 301, 302, 30
8,309...Input 303...Carry input 304.305...Output 1 306...Carry propagation control signal 307...
...Carry generation control signal 401.402...
Input 403... Carry input 404... Addition output 405... Carry output 406... Arithmetic unit 407... Carry Control signal generation section 408・
...Carry propagation control signal 409...
・Carry generation control signal 410... Carry control section

Claims (1)

[Claims] A first input pair of 1 and 2 bits, a second input pair of 2 bits, a third input input of carry, and 2 bits of 1. The first pair of outputs, the second output that outputs carry, the first pair of inputs, the second pair of inputs, and the binary values given to the third input are added, and the sum is added to the second output pair that outputs the carry. an arithmetic unit that outputs to one output pair; and a logical value of the lower bits of the first input pair and the lower bits of the second input pair are not equal to each other, and the upper bits of the first input pair and the second input pair are unequal to each other; A function that detects that the logical values of the upper bits of the pair are not equal to each other and outputs that information, and that the logical value of the lower bit of the first input pair and the lower bit of the second input pair are both 1. , and the logical value of at least one of the upper bits of the first input pair and the upper bits of the second input pair is 1, or the upper bits of the first input pair regardless of the state of the lower bits. detecting that the logic values of the upper bits of the second input pair and the second input pair are both 1;
a first logic circuit having a function of outputting the information; and a first logic circuit that outputs a logic value of 1 to the second output or a logic value of 0 to the second output depending on the output of the first logic circuit. , a second logic circuit having a function of controlling whether a logic value of a third input is propagated to a second output.