JPH08123662A - Adding method and adder - Google Patents

Abstract

PURPOSE: To decrease the number of necessary gates and speed up the addition of the adder by generating a carry signal for every three digits by 1st-4th NAND gates. CONSTITUTION: A NAND gate 101 NANDs a carry propagation signal pi (3>=i>=n) and a carry generation signal gi-1 to generate a signal I(pi gi-1 ). A NAND gate 102 NANDs carry propagation signals pi and pi-1 and a carry generation signal gi-2 to generate a signal I (pi , Pii-1 , pi-2 ). A NAND gate 103 NANDs carry propagation signals pi , pi-1 , and pi-2 to generate a signal I (pi , pi-1 , pi-2 ), which is outputted as a carry propagation signal pi ". A NAND gate 104 NANDs an inverted carry generation signal Igi , the signal I (pi pi-1 ), and the signal I (pi , pi-1 , pi-2 ) to generate a carry generation signal gi ". Consequently, the number of necessary gates can be decreased and the addition of the adder is speeded up.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an addition method and an adder, and more particularly to a binary addition method and an adder using a carry look ahead method.

[0002]

2. Description of the Related Art In a conventional general multi-bit adder,
IPSJ, Information Processing Handbook, 354 pages,
CLA (C described in Ohmsha (1989), etc.
An adder of an early look-ahead (carry look ahead) method is widely adopted. In this method, the carry signal is not determined by the lower order operation, but basically, for each n digits to be operated, the addition is performed by using the carry signal directly obtained from the lower order digit. Is the way.

The carry signal c _{i at} the arbitrary digit, i-th digit, to be operated is the addend and augend of the i-th digit x _i ,
When y _i , the carry propagation signal of the i-th digit, and the carry generation signal are p _i and g _i , respectively, they are expressed by the following equation.

P _i = x _i o + y _i g _i = x _i y _i c _i = (x _i y _i ) + (x _i o + y _i ) c _i-1 = g _i + p _i c _i-1 ………………………………………………… (1) Here, the symbol ○ + indicates exclusive OR.

Further, in a multi-bit high-speed adder, a carry signal is propagated to a carry signal propagating every two digits in a BLC (Binary Look-ahead Ca).
rry: Binary look-ahead carry) type adder is used.

According to this method, an arbitrary digit to be operated, i-th
The carry signal c _i of the digit is represented by the following equation using the carry signal c _i-2 of the (i−2) th digit.

C _i = g _i + p _i g _i-1 + p _i p _i-1 c _i-2 = g _i '+ p _i ' c _i-2 (2) That is, the first and second terms (= g _i + p _i g _i-1 ) is a new carry generation signal g _i ', and the part (= p _i p _i-1 ) excluding c _i-2 of the third term is a new carry propagation signal p _i '
By redefining the following, the carry signal is propagated simultaneously every two digits.

According to this method, in the addition of n digits, the delay time when the highest carry signal c _n is generated is suppressed to the order of log ₂ n, and the number of digits is longer than that of the CLA method. The addition can be performed at high speed.

Referring to FIG. 2 which is a circuit diagram of a circuit for generating a carry generation signal g _i 'and a carry propagation signal p _i ' of a conventional BLC type adder, this conventional adder is O
An R-NAND gate 301 and a NOR gate 302 are provided.

The operation of the conventional addition method and adder will be described below with reference to FIG.
The gate 301 receives the supplied inverted carry generation signal I
(Inverted) g _i−1 and O of the inverted carry propagation signal Ip _i
An R operation is performed, and a NAND operation is performed on the OR operation value and the inverted carry generation signal Ig _i to generate a carry generation signal g _i ′. NOR gate 302 performs a NOA operation on inverted carry propagation signal Ip _i and inverted carry propagation signal Ip _i−1 to generate carry propagation signal p _i ′.

[0011]

Since the above-described conventional addition method and adder carry the carry signal every two digits, the time required to obtain the highest carry signal in n-digit addition is log. There is a drawback that it cannot be less than ₂ n.

[0012]

The addition method according to the present invention uses two methods.
I-th digit (3 ≧ i ≧ 3) of each of the n n-digit (n ≧ 3) binary numbers
In the addition method using the carry generation signal generated by the logical product of the values of n) and the carry propagation signal generated by the exclusive OR of the values of the i-th digit, the carry propagation signal of the i-th digit and the ( A first AND is calculated with the (i-1) -digit carry generation signal, and the i-th carry carry signal, the (i-1) -th carry carry signal, and the (i-2) -th carry carry are calculated. A second logical product of the generated signal and the carry propagation signal of the i-th digit, the carry propagation signal of the (i-1) th digit, the carry propagation signal of the (i-2) th digit, and the (i) th digit are calculated. −
3) Calculate the third logical product with the carry signal of the digit,
It is characterized in that the carry signal of the i-th digit is generated by calculating the logical sum of the carry generation signal of the digit and the first, second and third logical products.

The adder of the present invention has two n digits (n ≧ 3).
A carry generation signal generated by the logical product of the values of the i-th digit (3 ≧ i ≧ n) of each of the binary numbers and a carry propagation signal generated by the exclusive OR of the values of the i-th digit. (I
-3) In an adder including a carry look-ahead circuit for directly generating a carry signal of an i-th digit from a carry signal of a carry, the carry look-ahead circuit includes a carry propagation signal of the i-th digit and a (i-1) -th digit. A 2-input NAND gate for generating a first NAND circuit in response to the supply of the carry generation signal of the above, the carry propagation signal of the i-th digit, the carry propagation signal of the (i-1) th digit, and the carry propagation signal of the (i) th digit. -1) a first 3-input NAND gate for generating a second NAND circuit in response to the supply of the carry generation signal of -1 digit, the carry propagation signal of the i-th digit, and the (i-1) -th digit Second three-input NAND for generating a third NOR as the i-th digit carry-propagation signal of the next digit in response to the supply of the carry-propagation signal and the (i-2) -th digit carry-propagation signal. The gate, the negative logic of the carry generation signal of the i-th digit, and It is configured to include a third three-input NAND gate to generate a fourth NAND is carry generation signal in response to the supply of the first and second NAND.

[0014]

EXAMPLES Referring now to Figure 1 showing a carry look ahead circuit for one bit embodiment of the present invention in the circuit diagram, the adder of the present embodiment shown in this drawing, the carry propagation signal p _i A NAND operation with the carry generation signal g _i-1 is performed to obtain the signal I (p _i
g _i-1 ), and N of the carry propagation signals p _i and p _i-1 and the carry generation signal g _i-2.
A NAND gate 102 that performs an AND operation to generate a signal I (p _i , p _i-1 g _i-2 ) and a carry propagation signal p _i ,
The NAND operation of p _i-1 and p _i-2 is performed and the signal I
NAND gate 103 that generates (p _i , p _i-1 p _i-2 ) and outputs it as carry propagation signal p _i ″, inverted carry generation signal Ig _i , signal I (p _i g _i-1 ) and signal I NAND gate 104 that performs a NAND operation with (p _i , p _i-1 g _i-2 ) to generate carry generation signal g _i ″
With.

Next, the operation of the present embodiment will be described with reference to FIG. 1. The NAND gate 101 has the carry propagation signal p _i of the i-th digit and the carry generation signal g _i of the i−1 th digit of the previous digit. _-1 and _-1 to perform a NAND operation to generate a signal I (p _i g _i-1 ). In addition, NAND gate 1
02 is the carry propagation signal p of the i-th digit and the (i-1) th digit.
NAND operation is performed in response to the supply of _i , p _i-1 and carry generation signal g _{i-2 of} the (i-2) th digit and signal I (p _i , p
_i-1 g _i-2 ) is generated. The NAND gate 103 performs the NAND operation of the supplied carry propagation signals p _i , p _i-1 and p _i-2 of the i-th digit, the i-1 th digit and the i-2 th digit to generate a signal I. (P _i p _i-1 p _i-2 ) is output as a carry propagation signal p _i ″. Further, the NAND gate 104 receives the inverted carry generation signal Ig _{i of} the i-th digit and the signal I (p _i). g _i-1 ) and the signal I
A NAND operation with (p _i , p _i-1 g _i-2 ) is performed to generate a carry generation signal g _i ″.

As described above, the carry look-ahead circuit of the adder according to the present embodiment has the carry signal c _i of the i-th digit and the carry signal c of the i-3 th digit obtained by further expanding the equation (2). It corresponds to the relational expression with _i-3 .

C _i = g _i + p _i g _i-1 + p _i p _i-1 g _i-2 + p _i p _i-1 p _i-2 c _i-3 = g _i ″ + p _i ″ c _i-3 ... ...................................................... (2) _{where, g i "= g i +} p i g i-1 + p i p i-1 g i-2, p i" = P _i p _i-1 p _i-2 Therefore, by using the circuit of the present embodiment,
The carry signal of the digit is obtained directly from the carry signal of the (i-3) th digit. By foreseeing the carry signal every three digits in this way, the required number of gate stages can be reduced, so that the addition can be speeded up. Specifically, the carry propagation delay can be reduced to about log ₃ n with respect to the addition of n digits.

The OR of FIG. 3 in the conventional BLC adder.
A ratio of a NAND composite gate 301 to a certain reference delay time (for example, a delay time of a constant size inverter having a constant load capacitance formed under the same process condition) is a
And the 3-input NAND gate 10 of the adder of the present embodiment.
If the above ratio at 2, 103 and 104 is b,
The effect of delay time reduction on the carry propagation delay of the conventional BLC adder of the adder of the present embodiment is expressed by the following equation.

(Alog ₂ n) / (2blog ₃ n) (3) Therefore, the adder according to the present embodiment is different from the conventional BLC adder in that Under the condition of a / b> 1.26, the larger n is, the higher the speed becomes.

Next, referring to FIG. 2 which is a block diagram showing a second embodiment of the present invention, the adder of the present embodiment shown in this figure is an 8-digit adder and is supplied to the input terminals 1 and 2. Was done 2
Carry propagation signal p from eight 8-digit binary numbers (the following two numbers)
1 and a carry generation signal g, a pg signal generation circuit 201, a sum generation circuit 202 that generates the sum of two numbers and outputs the sum to the output terminal, and the carry look-ahead circuits 213 to 2 in FIG.
18, buffers 203 to 206, AND-OR gates 207 to 210, and carry generation signals which are circuits obtained by optimizing unnecessary functions among the functions of the carry look-ahead circuit of FIG. 1 according to the input value. carry generation signal generation circuits 211 and 2, which are partial circuits that generate g _i ″.
12 and.

The operation of the present embodiment will be described with reference to FIG. 2. Two 8-digit 2's provided to the input terminals 1 and 2 are used.
In response to the supply of the base number, the pg signal generation circuit 201 generates a set of eight carry propagation signals p and carry generation signals g. The set of the carry propagation signal p and the carry generation signal g for each digit is carried by the carry look-ahead circuits 213 to 218.
And buffers 203 to 206, AND-OR gate 2
07-210, carry generation signal generation circuits 211, 21
2 and all carry signals are generated. All the carry signals thus obtained are added to the sum generation circuit 2
02, the sum generation circuit 202 generates the sum of two numbers in response to the supply of these carry signals, and outputs the sum to the output terminal.

Although the present invention has been described with reference to the embodiments,
The invention is not limited to this embodiment only. For example, instead of the carry look-ahead circuit of the present embodiment, as long as the circuit is intended for carry look-ahead, all the different circuit configurations that perform logical operations equivalent to those shown in FIG.
It is clear that the invention applies.

Further, the carry look-ahead circuit of the adder of the present embodiment is a logic circuit of positive logic input and positive logic output. However, even when the input or output is changed to negative logic and used in the adder, The invention can be applied without any trouble.

It is needless to say that the present invention can be applied only to a part of the carry look-ahead portion instead of being applied to all the portions of the carry propagation without departing from the gist of the present invention.

[0025]

As described above, the addition method and adder of the present invention are faster as the number of digits of the binary number to be added is larger than that of the conventional BLC adder. There is an effect that it is possible to speed up a high-precision arithmetic unit that requires.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a carry look-ahead circuit showing a first embodiment of an addition method and an adder of the present invention.

FIG. 2 is a block diagram showing a second embodiment of the addition method and adder of the present invention.

FIG. 3 is a circuit diagram showing an example of a carry look-ahead circuit of a conventional adder.

[Explanation of symbols]

 101-104 NAND gate 201 pg signal generation circuit 202 sum generation circuit 203-206 buffer 207-210 AND-OR gate 211,212 carry generation signal generation circuit 213-218 carry look-ahead circuit 301 OR-NAND gate 302 NOR gate

Claims (3)

[Claims] 1. A carry generation signal generated by the logical product of the values of the i-th digit (3 ≧ i ≧ n) of two n-digit (n ≧ 3) binary numbers and the value of the i-th digit. In an addition method using a carry propagation signal generated by exclusive OR, a first logical product of the carry propagation signal of the i-th digit and the carry generation signal of the (i-1) th digit is calculated, A second logical product of the i-th digit carry propagation signal, the (i-1) -th digit carry propagation signal, and the (i-2) -th digit carry generation signal is calculated to obtain the i-th digit carry propagation signal. A third logical product of the carry propagation signal of the (i-1) th digit, the carry propagation signal of the (i-2) th digit, and the carry signal of the (i-3) th digit is calculated, Carry generation signal and the first, second and third
An addition method characterized in that a carry signal of the i-th digit is generated by calculating a logical sum with the logical product of. 2. A carry generation signal generated by a logical product of the values of the i-th digit (3 ≧ i ≧ n) of each of two n-digit (n ≧ 3) binary numbers and the value of the i-th digit. In the addition method of directly generating the carry signal of the i-th digit from the carry signal of the (i-3) th digit using a carry propagation signal generated by exclusive OR, carry generation for generating the carry signal of the i-th digit A signal calculates a first logical product of the carry propagation signal of the i-th digit and the carry generation signal of the (i-1) th digit, and the carry propagation signal of the i-th digit and the (i-1) th digit of the carry propagation signal. A second logical product of the carry propagation signal and the carry generation signal of the (i-2) th digit is calculated, and a logical sum of the carry generation signal of the i-th digit and the first and second logical products is calculated. Carry propagation for directly generating the i-th digit carry signal Signal is generated by calculating a third logical product of the i-th carry carry signal, the (i-1) -th carry carry signal, and the (i-2) -th carry carry signal. A carry-look-ahead addition method characterized in that 3. A carry generation signal generated by a logical product of the values of the i-th digit (3 ≧ i ≧ n) of two n-digit (n ≧ 3) binary numbers and the value of the i-th digit. An adder having a carry look-ahead circuit that directly generates a carry signal of the i-th digit from a carry signal of the (i-3) th digit using a carry propagation signal generated by exclusive OR, in which the carry look-ahead circuit is A two-input NAND gate for generating a first NAND circuit in response to the supply of the carry propagation signal of the i-th digit and the carry generation signal of the (i-1) -th digit, and the carry propagation signal of the i-th digit And a first three-input NAND gate that generates a second NAND circuit in response to the supply of the carry propagation signal of the (i-1) th digit and the carry generation signal of the (i-1) th digit, The i-th digit carry propagation signal and the (i-1) -th carry carry signal When the (i-2) in response to the supply of the digit carry propagate signal second 3-input NAND to generate a third NOR a carry propagation signal of the i digit follows digit
A gate and a third three-input for generating a fourth NAND operation which is a carry generation signal in response to the supply of the negative logic of the i-th digit carry generation signal and the first and second NAND products. NAN
An adder comprising a D gate.