JPH06309153A - Multiplying circuit - Google Patents

Abstract

PURPOSE:To shorten computing time by outputting a computed result up to the time of a high-order part at a time when a carry signal on a low-order side is decided. CONSTITUTION:The computation of two carry signals when the carry signal from a low-order part Z10 exists and not are performed on the least significant bit Z by an output switching type full adder 6, and also, the computation of the sum signal of the two carry signals when the carry signal exist and not is performed. Also, two carry signals are outputted from the high-order parts Z12-Z14 higher than that by computing each carry signal at each digit by using the two carry signals from the low-order part, and also, the computation of the sum signal of its own digit is performed by the two carry signals. The computation of the sum signal of its own digit is performed at a most significant part Z15 by using the two carry signals from the low-order part Z14. When the carry signal at the low-order part Z10 is decided, the carry signal is fetched in the high-order parts Z11-Z15, and either sum signal of its own digit is outputted corresponding to the carry signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplying circuit which speeds up calculation.

[0002]

2. Description of the Related Art FIG. 9 shows a conventional 8-bit.times.8-bit multiplication circuit. This circuit is configured by combining a plurality of AND gates 1, a plurality of half adders 2, and a plurality of full adders 3.

As shown in FIG. 10, the half adder 2 includes a NAND gate 201, an exclusive OR gate 202, and an inverter 203.
Reference numeral 204 is an input terminal of two signals for addition of own digit, 205
Is a sum signal output terminal of its own digit, and 206 is a carry signal output terminal.

As shown in FIG. 11, the full adder 3 is composed of NAND gates 301 to 303, and exclusive OR gates 304 and 305. Reference numeral 306 is an input terminal of two signals for addition of its own digit, 307 is a carry signal input terminal from a lower part, 308 is a sum signal output terminal of its own digit, 30
Reference numeral 9 is a carry signal output terminal to the upper portion.

In the operation of the multiplication circuit shown in FIG. 9, each AND gate 1 performs a partial product of the multiplicands X _{0 to} X ₇ and the multipliers Y _{0 to} Y _7, and the result is the half adder 2 or full addition. Bowl 3
More specifically, the sum signal output of the own digit and the carry signal to the upper digit are determined from the carry signal from the lower digit and the addition result of the own digit. It is done in order.

However, in the multiplication circuit of this circuit configuration, its operation speed is greatly affected by the propagation speed of the carry signal from the lower digit, and it is difficult to increase the operation speed.

Therefore, in order to improve the calculation speed, as shown in FIG. 12, the CLA (Ca
It has been practiced to use Adder 4 with a rry Look Ahead).

As shown in FIG. 13, this CLA-added adder 4 has two adders 41 connected in series.
FIG. 14 is a diagram showing the adder 41.
1 is half adders 401 to 414 and NAND gates 415 to 415.
419 and an inverter 420.
421 to 424 are signal input terminals, 425 is a carry signal input terminal from a lower digit, 426 to 429 are sum signal output terminals, and 430 is a carry signal output terminal to an upper digit.

[0009]

However, in the configuration using the adder 4 with CLA, the operation speed can be improved to some extent as compared with the multiplier having the configuration shown in FIG. When the number increases, the calculation still takes time, and there is a problem that the speed cannot be increased.

The present invention has been made in view of the above points, and an object thereof is to provide a multiplier capable of performing high-speed multiplication operation.

[0011]

To this end, according to the present invention, each logical product circuit performs a partial product of a multiplicand and a multiplier by one bit, and each adder performs addition and carry of the partial product. In the multiplication circuit that obtains the multiplication result, the final stage of the addition stage of partial products is divided into an upper part and a lower part, and in each of the upper parts, in parallel with the calculation of the individual sum signal and carry signal of the lower part. An arithmetic operation is performed to obtain two kinds of sum signals with and without a carry signal from the lower part, and when the carry signal of the lower part is determined, the upper part according to the carry signal is determined. One of the individual sum signals of is determined.

[0012]

In the present invention, in the upper part of the adding stage of the partial products, two kinds of sum signals are calculated and waited while waiting for the arrival of the carry signal from the lower part. Compared with the conventional method of starting the calculation, the time required to obtain the calculation result can be significantly shortened and the overall calculation speed can be increased.

[0013]

EXAMPLES Examples of the present invention will be described below. FIG. 1 is a circuit diagram of a multiplication circuit of the embodiment. The same components as those described above are designated by the same reference numerals, and detailed description thereof will be omitted. Reference numeral 5 is an output switching type first full adder, 6 is an output switching type second full adder, and 7 is an output switching device.

As shown in FIG. 2, the output switching type first full adder 5 is composed of NAND gates 501 to 505, exclusive screw OR gates 506 to 508, transmission gates 509 and 510, and an inverter 511.

Reference numeral 512 is a signal input terminal for two signals for adding own digits, 513 is a carry signal input terminal when there is no carry signal from the lower part, and 514 is a carry signal from the lower part. In the case, a carry signal input terminal, 515 is a sum signal output terminal of addition of own digit, 516 is a carry signal input terminal of a lower part, and 517 is a carry signal output terminal when there is no carry signal from the lower part, Reference numeral 518 is a carry signal output terminal when there is a carry signal from the lower part.

In the output switching type first full adder 5, a sum signal of two signals input to the signal input terminal 512 and a signal of one carry signal input terminal 513, or the other carry signal input. The sum signal with the terminal 514 is output from the signal output terminal 515. At this time, which sum signal is to be taken is determined by the signal input to the carry signal input terminal 516.

As shown in FIG. 3, the output switching type second full adder 6 comprises a NAND gate 601, a NOR gate 602, an X-screw OR gate 603, transmission gates 604 and 605, and inverters 606 to 609. .

Reference numeral 610 is a signal input terminal of two signals for addition of own digit, 611 is a sum signal output terminal of addition of own digit, 61
2 is a carry signal input terminal of the lower part, 613 is a carry signal output terminal when there is no carry signal from the lower part, 614
Is a carry signal output terminal when there is a carry signal from the lower part.

In the output switching type second full adder 6, the non-inverted value or the inverted value of the coincidence signal of the signal input to the signal input terminal 610 is output from the sum signal output terminal 611. At this time, switching between the non-inverted value and the inverted value is performed by a signal input to the carry signal input terminal 612.

Next, the output switching device 7 is composed of transmission gates 701 and 702 and an inverter 703. 704 is a carry signal input terminal when there is no carry signal from the lower part, 705 is a carry signal input terminal when there is a carry signal from the lower part, 706 is a signal output terminal of its own digit, and 707 is a lower order This is a carry signal input terminal of the section.

In this output switcher 7, a signal input to one of the carry signal input terminals 704 and 705 is output to the signal output terminal 706 in response to a signal input to the carry signal input terminal 707.

[0022] Now, the multiplication circuit shown in FIG. 1, as in the prior art, each of the AND gates 1, calculates the partial products of the multiplicand X ₀ to X ₇ and the multiplier Y ₀ to Y _7, the partial products The half adder 2 or the full adder 3 adds each bit to obtain the multiplication results Z _{0 to} Z _15. The final stage of addition of partial products is the lower part of Z _{7 to} Z _10. It is divided into the upper part of Z _{11 to} Z ₁₅ .

Then, in parallel with the calculation of the sum signal of its own digit in the lower part of Z _{7 to} Z ₁₀ and the calculation of the carry signal to the upper part, the following calculation is performed in the upper part of Z _{11 to} Z _15. To do.

That is, at the least significant bit (Z ₁₁ ), the output switching type second full adder 6 outputs two carry signals with and without the carry signal from the lower part (Z ₁₀ ). In addition to the calculation, a sum signal of the two relevant digits is calculated when the carry signal is present and when it is not present.

Further, the upper part Z₁₂~ Z 7₁₄smell
Using two carry signals from the lower part,
Two carry signals are calculated by calculating each carry signal at each digit.
Signal and outputs the two carry signals.
Calculates the sum signal of digits.

In the uppermost part Z ₁₅ , the two carry signals from the lower part Z ₁₄ are used to calculate the sum signal of its own digit.

Then, when the carry signal at Z ₁₀ in the lower part is determined, the carry signals are taken in by the upper parts Z _{11 to} Z ₁₅ and any one of its own digits is taken according to the carry signal. The sum signal of is output.

As a result, when the carry signal at Z ₁₀ in the lower part is determined, the result of the operation performed by the upper part up to that point is output, so that the overall operation time can be shortened and the high speed operation can be achieved. Is possible.

In the example of FIG. 1, the lower part is 8 bits.
The lower part and the upper part are distributed so that 11 bits and the upper part are 12 bits to 16 bits, but when the number of output bits is smaller or larger than that, the operation speed of the lower part and the upper part is calculated. If the values are set to be almost the same, the calculation speed can be maximized.

Further, when the number of stages in the upper part increases or decreases, the number of output switching type first full adders 5 may be increased or decreased to cope with the increase or decrease. Further, the multiplication speed can be further improved by using the BOOTH algorithm to reduce the number of partial products, or by using the addition of partial products in combination with the method of configuring the WALLACE tree.

FIG. 5 shows a modification in which the CLA-equipped adder 41 (see FIGS. 13 and 14) is used for the lower parts Z _{7 to} Z ₁₀ in FIG. In the case of FIG. 1, steps Z ₇ -Z ₁₀
Which required the calculation of the sequential carry over
In FIG. 5, since carry is carried out from Z _{10 in} parallel with the calculation of Z _{7 to} Z ₁₀ , the calculation speed can be increased.

FIG. 6 is a circuit diagram of a modification of the output switching type first full adder 5 shown in FIG. Here, seven inverters 519 to 525, thirteen transmission gates 526 to 538, and one PMOS transistor 539 are included.

Comparing this with the circuit shown in FIG. 2,
The number of transistors used is 56 as shown in FIG. 2 (10 transistors are used for the exclusive screw OR gate).
There are four NAND gates, four inverters, two inverters, and two transmission gates. ), While
The number shown in FIG. 6 is reduced by 41 and 15.

The operating speed is also the carry signal input terminal 5
The path from 13, 514 to the carry signal output terminals 517, 518 includes two NAND gates, whereas the former one shown in FIG. 2 includes two NAND gates. So it's faster.

FIG. 7 is a modification of FIG. 6, and the PMO of FIG.
Instead of the S transistor 539, an NMOS transistor 540 is used, the inverter 520 is deleted, and another inverter 541, 542 is used.

FIG. 8 is a circuit diagram of a modification of the output switching type second full adder 6 shown in FIG. Here, seven inverters 615-621, six transmission gates 622-627, one PMOS transistor 628,
It is composed of one NMOS transistor 629.

Comparing this with the circuit shown in FIG. 3,
The number of transistors used is 30 as shown in FIG. 3 (the transistors used are 10 xixor OR gates, 4 NAND gates, 4 NOR gates, 2 inverters and 2 transmission gates). 8) and 2 are shown in FIG.
Only the number is decreasing.

[0038]

As described above, according to the present invention, when the carry signal in the lower part is determined, the result of the operation performed by the upper part up to that time is output. Has the advantage that it can be shortened and high-speed operation becomes possible.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a multiplication circuit according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an output switching type first full adder.

FIG. 3 is a circuit diagram of an output switching type second full adder.

FIG. 4 is a circuit diagram of an output switch.

FIG. 5 is a circuit diagram of a multiplication circuit according to another embodiment.

FIG. 6 is a circuit diagram of another example of the output switching-type first full adder.

FIG. 7 is a circuit diagram of still another example of the output switching-type first full adder.

FIG. 8 is a circuit diagram of another example of the output switching type second full adder.

FIG. 9 is a circuit diagram of a conventional multiplication circuit.

FIG. 10 is a circuit diagram of a half adder.

FIG. 11 is a circuit diagram of a full adder.

FIG. 12 is a circuit diagram of another conventional multiplication circuit.

FIG. 13 is a block diagram of an adder with CLA.

FIG. 14 is a circuit diagram of an adder with CLA.

[Explanation of symbols]

1: AND gate, 2: Half adder, 3: Full adder, 4:
Adder with CLA, 5: Output switching type first full adder, 6:
Output switching type second full adder, 7: output switching unit.

Claims (2)

[Claims] 1. A multiplication circuit in which a multiplicand and a multiplicand of each bit are subjected to a partial product in each logical product circuit, and the partial products are added and carried by individual adders to obtain a multiplication result. The final stage of the addition stage of is divided into an upper part and a lower part, and in each of the upper parts, a calculation is performed in parallel with the calculation of each sum signal and carry signal of the lower part, and the digit from the lower part is calculated. Two kinds of sum signals with and without an upstream signal are obtained, and at the time when the carry signal of the lower part is determined, one of the individual sum signals of the upper part is determined according to the carry signal. A multiplication circuit characterized in that 2. The multiplication circuit according to claim 1, wherein the lower part is composed of an adder with CLA.