JPS633342B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a scan register configuration method in a logic device that holds the output of a logic circuit and has at least two registers that operate independently.

Select a logic device, for example, a register (scan register) included in one LSI, input serial test data to the scan register from the outside through a scan path, and send the data in the scan register to the logic circuit of the LSI. It is done to test the logic circuit by inputting it. In order to perform this test, it is necessary to configure a register to which the outputs of the logic circuit are applied in parallel as a scan register. Conventionally, this scan register was configured as follows.

For example, in a logic device such as an LSI, as shown in FIG. 1, if the output of a logic circuit 1 is stored in parallel in a register 6 consisting of flip-flops 2 to 5 operated by a clock. , as shown in FIG. 2, each bit output of logic circuit 1 is supplied to selection circuits 7 to 10, and each output of selection circuits 7 to 10 is supplied to flip-flops 2 to 5, respectively. The outputs are flip-flops 11 to 14 which operate on a clock exclusive to the clock.
supplied to The outputs of flip-flops 11-13 are supplied to the other input sides of selection circuits 8-10, respectively. The other input side of the selection circuit 7 is connected to an external terminal 15, and the output side of the flip-flop 14 is connected to an external terminal 16. Selection circuit 7-1
0 selects one of the two inputs according to the control signal at the terminal 17 and outputs it.

Normally, the output of logic circuit 1 is selected by selection circuits 7-10, inputted in parallel to flip-flops 2-5, and supplied to other logic circuits not shown. When a control signal for setting the scan mode is given to the terminal 17, the selection circuit 7 sets the external terminal 15 to
Selection circuits 8-10 are flip-flops 11-13.
The test data from the external terminal 15 is input to the flip-flop 2 by the clock, and then shifted to the flip-flop 11 by the clock.Then, when the clock is applied, the data in the flip-flop 11 is transferred to the selection circuit 8. The data is shifted to the flip-flop 3 through the input terminal 3, and the same operation is performed thereafter, and finally the data is output to the external terminal 16. In this way, flip-flops 2-5 (register 6) are configured as scan registers.

In this way, conventionally, in order to convert register 6 into a scan register, it is necessary to add selection circuits 7 to 10 and flip-flops 11 to 14, which has the disadvantage of requiring a relatively large amount of metal. Note that when flip-flops 2 to 5 are directly connected in series, the contents of flip-flop 2 reach flip-flop 5 in one clock and cannot operate as a scan register.

<Summary of the Invention> An object of the present invention is to provide a method of constructing a scan resistor that can construct a scan resistor by adding a small amount of metal objects.

Logic devices generally have registers that operate independently, that is, with different operating clocks. According to the present invention, a scan register is constructed by alternately connecting these independently operating registers in series for each bit.

<Embodiment> FIG. 3 shows an embodiment of the scan register construction method according to the present invention. Logic circuits 20 and 30 are provided in one logic device, and the output of logic circuit 20 is held in a register 29 consisting of flip-flops 25 to 28, and
The output of the logic circuit 30 is held in a register 39 consisting of 38. Flip-flops 25-28 are operated by a clock, and flip-flops 35-38
is operated by a clock, that is, it operates independently of flip-flops 25-28.

In this invention, a first
Selection circuits 21 to 24 are inserted, and logic circuit 3
Second selection circuits 31-34 are inserted between the output side of 0 and flip-flops 35-38, respectively. The external terminal 15 is connected to the other input side of the first selection circuit 21, and the output sides of flip-flops 35-37 are connected to the other input sides of the first selection circuits 22-24, respectively. Second selection circuits 31 to 34
The output sides of flip-flops 25 to 28 are respectively connected to the other input side of flip-flop 3.
The output side of 8 is connected to an external terminal 16. The inputs of the selection circuits 21 to 24 and 31 to 34 are switched by a control signal at the terminal 17.

A control signal is given to the external terminal 17 to select the selection circuit 21.
24 and 31 to 34 are set to the scan mode, the data at terminal 15 is input to flip-flop 25 by the clock, the data from flip-flop 25 is shifted by the clock to flip-flop 35 through selection circuit 31, and then the data from flip-flop 35 is input by the clock to flip-flop 35. Data is selection circuit 2
2 to flip-flop 26;
Thereafter, in the same manner, the data passes alternately through the flip-flops of the registers 29 and 39 and is output to the terminal 16. In other words, registers 29 and 39 constitute a scan register. Note that each output of flip-flops 25 to 28 constitutes each bit output of register 29, and each output of flip-flops 35 to 38 constitutes each bit output of register 39.

<Effects> As described above, according to the present invention, in order to convert the register 29 consisting of flip-flops 25 to 28 and the register 39 consisting of flip-flops 35 to 38 into scan registers, the selection circuits 21 to 2 are used, respectively.
This can be achieved by simply adding 4, 31 to 34, and the first
According to the conventional construction method shown in the figure, the amount of construction hardware can be reduced compared to the case where each register is further provided with the same number of flip-flops as the flip-flops that constitute it.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing a logic circuit and its output register, Fig. 2 is a diagram showing a scan register configured by the conventional method of the register shown in Fig.
The figure is a diagram showing an embodiment of the scan register configuration method according to the present invention. 20, 30: logic circuit, 21-24, 31-3
4: Selection circuit, 25-28: Flip-flop operated by clock, 35-38: Flip-flop operated by clock, 29, 39: Register.

Claims (1)

[Claims] 1. In a logic device that holds the output of a logic circuit and has at least two registers that operate independently, a first selector is provided for each bit of the first register, and the first selector corresponds to the first register. A second selector is provided for each bit of the second register, and a second selector is provided for each bit of the second register. The second selector selects either the output of the logic circuit corresponding to the second register or one bit output of the first register. 1. A scan register configuration method comprising controlling two selectors to alternately connect a first register and a second register in series for each bit to configure one scan register.