JPH0619730A - Automatic switch check system for parity - Google Patents

Abstract

PURPOSE:To provide a parity check system by which the selection condition of a parity additional side and that of a parity check side are set to be coincident without fail on the parity automatic switch check system of transmission/ reception data. CONSTITUTION:The error detection system of transmission/reception data, in which a parity generation part 11 and a selector 12 selecting one result concerned are provided on the transmission side of data, and a parity generation part 21 and a selector 22 selecting one result concerned are provided for the reception side of data is provided with a code detection part 13 which code- detects data becoming the object of parity generation, adds a code detection result concerned to the selector 12 and automatically switches a parity code in the transmission side, and a code detection part 24 which code-detects reception data, adds the code detection result concerned to the selector 22 and automatically switches the parity code in the reception side.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for automatically checking parity of transmitted / received data.

[0002]

2. Description of the Related Art A parity check method will be described below with reference to FIG. FIG. 5 is a diagram showing the configuration of a conventional example circuit.

In FIG. 5, the parity addition side is composed of a parity generator 11 and a selector 12. The parity check side is composed of a parity generation unit 21, a selector 22 and an alarm detection unit 23.

In order to improve reliability in data communication, a parity check is carried out. In the conventional parity check, however, it is decided in advance whether the odd number or even number should be added / checked between the parity addition and the check. Must be

In this case, of course, a check error occurs unless the settings (even or odd) on the addition side and on the check side match. First, the parity generation unit on the parity addition side
At 11, the parity of the transmission data is checked, and the check result is output as Even and Odd.

[0006] Here, "Even" means "1" when the number of "1" s in the transmission data is an even number, and "0" when the number of "1s" in the transmission data is an odd number. This is the set output.

Odd is set so that it becomes "0" when the number of "1" s in the transmission data is an even number, and "1" when the number of "1s" in the transmission data is an odd number. Output.

Next, the Eve output from the parity generation unit 11
The result of the parity check of the output of n or the output of Odd is selected by the additional parity selection signal input to the selector 12, and is sent to the parity check side as a parity bit to be transmitted.

Parity check side parity generator 21
Checks the parity of the transmitted data and the parity bit, and E
Output both ven and Odd results.

Next, both the results of the parity check of the parity generator 21 are selected according to the check parity selection signal applied to the selector 22 and output to the alarm detector 23. Here, when the selector 12 on the parity addition side selects Even, the number of '1' becomes odd between parity addition and parity check.

Therefore, in the alarm detector on the parity check side, when "1" is defined as "alarm", the check parity selection signal of the selector 22 must be set to select Even.

At this time, if the selector 22 selects Odd, an "alarm" is always detected.

[0013]

Therefore, in the conventional automatic parity switching check method, the selection conditions on the parity addition side and the parity check side must be matched, and if they do not match, an alarm occurs. is there.

It is an object of the present invention to provide a parity check system that always matches the selection conditions on the parity addition side and the parity check side.

[0015]

In order to achieve the above object, as shown in FIG. 1, a parity generator for outputting an even / odd parity check of data to a data transmitting side.
11 and a selector that selects one of the parity checks
12, a parity generation unit 21 that performs a parity check that combines the received data and the additional parity and a selector 22 that selects one of the parity checks are provided on the data reception side to detect an error in transmission / reception data. In the system, a code detection unit 13 is provided on the transmission side, which performs code detection of the data to be parity-generated, adds the code detection result to the selector 12, and automatically switches a parity code (even / odd). , The receiving side is provided with a code detecting section 24 which performs code detection of received data and adds the code detection result to the selector 22 to automatically switch the parity code (even / odd number). It is configured to perform matching parity switching.

[0016]

In the present invention, as shown in FIG. 1, the parity addition side is provided with a code detection section 13 for detecting a constant code, and the parity check side also detects a code same as the parity addition side. The detection unit 24 is provided.

When a certain data A arrives at the parity addition side, even parity is added after the data A under the control of the code detection unit 13, and the data A comes at the parity check side. If the code detector 24
The data A and thereafter are switched to the even parity check by the control.

Further, when another certain data B arrives at the parity addition side, the data B is controlled by the code detection unit 13.
After that, odd parity is added, and when the data B comes to the parity check side, the code detector 24 controls the data B to be switched to the odd parity check.

Therefore, the setting on the addition side and the setting on the check side can be automatically matched, and it is possible to prevent the occurrence of an alarm due to an erroneous setting of parity.

[0020]

Embodiments of the present invention will be described in detail below with reference to FIGS. FIG. 2 is a diagram showing the configuration of an embodiment circuit of the present invention. 3 is a diagram (No. 1) showing the timing of the circuit according to the embodiment of the present invention, and shows the timing on the parity addition side. FIG. 4 is a diagram (No. 2) showing the timing of the circuit according to the embodiment of the present invention, and shows the timing on the parity check side.

In FIG. 2, reference numerals 11, 12, and 13 are circuits provided on the parity addition side. 11 is a parity generation unit, and 12
Is a selector having two AND gates 12a and 12c, an inverter 12b and an OR gate 12d. Further, 13 is a code detection unit, and the code detection unit 13 has a NAND gate.
13a, 13c and OR gate 13b, 13d and AND gate 13e, 13f
And a flip-flop (FF) 13g.

Then, the code detection unit 13 determines that some data A
This is for detecting (data'AA 'in this embodiment) and certain other data B (data'55' in this embodiment), and the selector 12 uses even parity and odd parity based on the detection result. Performs a logical operation between parities.

Further, 21, 22, 23, and 24 are circuits provided on the parity check side, 21 is a parity generation unit, 22 is a selector, and 23 is an alarm detection unit. Further, reference numeral 24 is a code detection unit, which has the same configuration and operation as the code detection unit 13.

In FIG. 3, (a) is 8-bit data D7 to D0 input to the parity addition side, and (b) is FF13.
A set (S) input of g, a reset (R) input of FF13g, (c) is a Q output of FF13g which is a parity selection signal.

Note that (e) is the Even of the parity generator 11.
(ΣE) is an even parity that is an output, and (f) is an odd parity that is an Odd (ΣO) output of the parity generation unit 11.
Further, (g) is a parity bit output from the selector 12 provided on the parity addition side.

In FIG. 4, (h) is the data D7 to D0 input to the check side, and the data D7 to D0 (a). (i) is a parity bit, and the additional parity
(g).

Note that (j) is the Even of the parity generator 21.
(ΣE) is an even parity that is an output, and (k) is an odd parity that is an Odd (ΣO) output of the parity generation unit 21.
Also, (l) is the code detection unit provided on the parity check side.
This is the parity selection signal output from 24. And (m)
Is an input of the alarm detector 23.

As shown in FIGS. 2, 3, and 4, parity generation / checking and code detection are performed on 8-bit data from the data transmission source. 2 and 3, first, the parity generator 11 generates two types of parity, that is, even parity (e) and odd parity (f) for the data D7 to D0 (a), and the code detector 13 outputs the data D7. ~ D
For example, code detection of '55'and'AA'in 0 (a) is performed, and the detection result is S input (b) and R input of FF13g.
Add as (c). In the following, this logic will be explained in detail.

The data D7 to D0 (a) are 8-bit code data such as'AA ',' 08 '...' 55 '. Where A, 0, 8, 2 ... 5
Are hexadecimal numbers. The relation between decimal numbers, data D7 to D0, and hexadecimal numbers will be briefly described below.

[0030]

[Table 1]

That is, the code of "55" is "01010101",
The code of'AA 'is the inverted code of' 55 ',' 1010
It is represented by 1010 '.

Data D7 to be input to the code detection unit 13
When the code of D0 is '55', the inputs of NAND gate 13a and OR gate 13b are all '1'.
The output of the NAND gate 13a becomes "0" and the output of the OR gate 13b becomes "1".

On the other hand, the NAND gate 13c and the OR gate 13d
All the inputs of "0" come to be aligned, and the NAND gate 13
The output of c becomes "1" and the output of the OR gate 13b becomes "0". Therefore, when the code is "55", the output (b) of the OR gate 13e becomes "0", and the "0" is added as the S input of the FF13g. The R input of the FF 13g, which is the output (c) of the OR gate 13f at this time, maintains "1".

Similarly, the codes of the data D7 to D0 are'A
If it is A ', the R input of FF13g becomes'0', and FF
The S input of 13g keeps '1'. If S of FF13g
When the input (b) becomes '0'('55' detected), FF13g
Is set to "0" of the S input (b) and the Q output (d) becomes "1", and the logic of the selector 12 selects the odd parity (f) output by the parity generation unit 11.

The R input (c) of FF13g is "0" (
When'AA 'is detected, FF13g is reset and Q
The output (d) becomes "0", and the logic of the selector 12 selects the even parity (e) output by the parity generation unit 11.

As a result of the above logic, the additional parity (g) output from the selector 12 becomes "0" as the even parity (e) if the data (a) is "AA". If the data (a) is '08', the odd parity (f) is '1'
If the data (a) is "55", the odd parity (f) is "1".

Next, on the data receiving side, as shown in FIG. 4, 8-bit data (h) from the transmitting side and the parity bit are sent.
Performs parity check and code detection for (i). As with the transmission source, the parity generation unit 21 generates two types of parity, even parity (j) and odd parity (k),
The selector 22 selects either the even parity (j) or the odd parity (k) according to the selection signal (l) from the code detector 24 and outputs it as the input (m) of the alarm detector 23.

[0038]

As is apparent from the above description, according to the present invention, in the parity check of data transmission, the transmitting side (parity adding side) and the receiving side (parity check side).
It is possible to automatically match the even / odd setting of, and it is possible to prevent erroneous setting of both.

Further, by switching generation / checking of even / odd parity for each specific code, more detailed data check can be performed, and there is an effect that it greatly contributes to improvement of reliability in data communication. .

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit of a principle configuration of the present invention.

FIG. 2 is a diagram showing a configuration of an embodiment circuit of the present invention.

FIG. 3 is a diagram (No. 1) showing the timing of the circuit according to the embodiment of the present invention.

FIG. 4 is a diagram (No. 2) showing the timing of the circuit according to the embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional example circuit.

[Explanation of symbols]

 11 is a parity generation unit 12 is a selector 13 is a code detection unit 21 is a parity generation unit 22 is a selector 23 is an alarm detection unit 24 is a code detection unit

Claims (1)

[Claims] 1. A parity generator (11) for outputting an even / odd parity check of data to a data transmission side,
Provided with a selector (12) for selecting one of the parity checks, and on the data receiving side, a parity generation unit (21) for performing a parity check combining the received data and the additional parity.
And a selector (2
2) is provided to detect an error in transmission / reception data, the transmission side performs code detection of the data that is the target of parity generation, and outputs the code detection result to the selector.
In addition to (12), a code detection unit (13) that automatically switches the parity code (even / odd number), and the reception side performs code detection of received data, and outputs the code detection result to the selector (22). In addition, a code detection unit (24) that automatically switches the parity code (even / odd)
The automatic parity switching check method is characterized in that parity is switched between the transmitting side and the receiving side so as to perform the same parity switching.