JPH0474234A - Simulation method for semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain the simulation with high accuracy by setting a MOS transistor TR gate in a high impedance state and using the signal value that is precedently calculated and stored by one step as a node output signal. CONSTITUTION:When the data DA and a signal A are kept at H levels with the data DB and a signal B kept at L levels respectively, a gate 12 opens and an output signal Vb is set at an L level. Meanwhile a gate 11 closes and is set in a Z floating state. Therefore the signal of a node 13 is calculated and stored at an L level based on the dot input ZB set at an L level at a gate 15. Then both data DA and DB are changed to the L and H levels respectively. Thus the input ZA kept in a Z floating state and the input ZB kept at an H level are inputted to a Z dot 14. The signal of the node 13 is calculated and stored at an H level based on the input ZB. Furthermore both gates 11 and 12 are set in the Z floating state respectively when the DA and B are changed to H levels together with the DB changed to an L level respectively. Thus an output signal VOUT is obtained since the signal is set at an H level at a node 14 precedent by one step.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a method for simulating a semiconductor integrated circuit, more specifically, a method for simulating a semiconductor integrated circuit including a selector made of a MOS transistor gate, and provides a dynamic memory function with a short processing time and a simple method. In order to be able to perform simulations that are consistent with actual operation and to improve the failure detection rate, the output terminals of multiple MOS transistor gates are connected to one node, and each MO3 transistor gate is In a semiconductor integrated circuit comprising a selector that appropriately selects an output signal from each gate and outputs it to the node, a logic value other than a high impedance state is transmitted from at least one of the MOS transistor gates to the node. When an output signal of Instead of the impedance output signal, a previously calculated and stored signal value is used as the node output signal.

[Industrial Field of Application] The present invention relates to a method of simulating a semiconductor integrated circuit, and more particularly to a method of simulating a semiconductor integrated circuit including a selector made of a MOS transistor gate.

In recent years, as LSIs have become larger and faster, selectors using MOS transistor gates have come into widespread use. Such a selector has a dynamic memory function due to the MOS transistor, etc., and fault simulation that takes this function into consideration is becoming necessary in order to increase the fault detection rate.

[Prior Art] Conventionally, in a selector using transmission gates made of, for example, MOS transistors, the output terminals of a plurality of transmission gates are connected to one node, and each transmission gate is selected as appropriate. Data output via a transmission or output from a node. The connection point between the output terminal of each transmission gate and a node (hereinafter referred to as a Z dot) has three states: an H level, an L level, and a high impedance state, depending on the state of each transmission gate.

In a failure simulation of an MO8LSI circuit equipped with such a selector, even though the MOS transistor has a dynamic memory function, it is treated as a static circuit without considering the operation based on that function.

[Problem to be Solved by the Invention] However, when a high impedance state is input to the Z dot that can take the three states (when each transmission gate becomes a high impedance state), the output of the Z dot is Z in relation to
Although the signal value stored by the dynamic memory function of the dot is output during actual operation, a high impedance signal is output in the simulation, which differs from the actual operation.

Therefore, in the MO3L81 circuit, actual detectable failures cannot be detected, resulting in a decrease in the failure detection rate.

Further, in order to approximate the actual operation, it is possible to perform a simulation that takes the signal strength into account, but this has the problem of requiring an enormous amount of processing time and complicating the processing.

The present invention has been made to solve the above-mentioned problems, and its purpose is to be able to perform simulations that are consistent with actual operations, taking into account dynamic memory functions, in a short and simple manner with a short processing time. An object of the present invention is to provide a simulation method for semiconductor integrated circuits that can improve the failure detection rate.

[Means for Solving the Problems] FIG. 1 is a flowchart illustrating the present invention in detail.

First, in a semiconductor integrated circuit, the output terminals of multiple MOS transistor gates are connected to one node, and each
It is determined whether the output signal outputted through the O8I-transistor gate is a selector that appropriately selects the output signal outputted through the transistor gate and outputs it to the node. That is, in relation to each MOS transistor gate, it is determined whether a connection point (Z dot) between the output terminal of each gate and a node or a point having a dynamic memory function (gate in a broad sense) is determined.

When it is determined that the Z dot (gate) has a dynamic memory function, the output signal of each MO3 transistor gate is calculated based on the operation pattern data at that time. Then, when at least one of the MOS transistor gates is an output signal of a logical value other than the no-impedance state, the signal value of the logical sum of each output signal at that time excluding the output signal of the high-impedance state is stored. and the output signal of the node.

On the other hand, when all the MOS transistor gates are in the /S impedance state, the previously calculated and stored signal value is used as the output signal of the node instead of the output signal of the no h impedance.

[Function] With the above configuration, when the output signals of each gate that are input as input signals to the Z dot having a dynamic memory function in relation to the MO8t transistor gate in the previous stage are all brought into a no-impedance state by calculation, The signal value stored by the dynamic memory function at the previous Z dot becomes the output signal of the node.

Therefore, the simulation corresponds to the actual operation, and accurate and highly accurate simulation is possible.

[Embodiment] An embodiment of a semiconductor integrated circuit simulation method embodying the present invention will be described below with reference to the drawings.

For convenience of explanation, a selector composed of two transmission gates 11 and 12 as MOS transistor gates shown in FIG. 2 will be used for explanation. Note that both transmission gates 11 and 12 are known P-channel MOS transistors.
It consists of a transistor, an N-channel MOS transistor, and an inverter circuit, and both gates 11 and 12
The output terminals of are connected to one node 13 to each other.

Also, one transmission gate (hereinafter referred to as the first gate) 11 transmits data DA based on the control signal A, and the other transmission gate (hereinafter referred to as the second gate) 12 transmits the data DB based on the control signal B. Output.

Both gates 11 and 12 receive a control signal A at H level,
When B is input, it becomes a high impedance state (hereinafter referred to as Z float), and the L level control signals A,
When B is input, data DA and DB signals are output as output signals Va and Vb, respectively. Also, both gates 11
．． Since 12 is composed of MO3t-transistor,
In relation to both gates, its output terminal and node 13
The connection point (hereinafter referred to as Z dot) 14 has a dynamic memory function, and when both gates 11 and 12 become Z floats, the state of the output signal of the previous node 13 is not discharged and remains in that state. will be retained.

Now, assuming that the Z dot 14 is one gate 15, a simulation operation will be described when control signals A, B and data DA, DB shown in FIG. 3 are output.

During time t2 to t3, data DA and control signal A are at H level, and data DB and control signal B are at L level. At this time, since the second gate 12 is opened, the output signal vb of the second gate 12 becomes the value of the data DB, that is, the L level. On the other hand, since the first gate 11 is closed, it becomes a Z-float state. Therefore, the dot input ZA in the Z floating state and the dot input ZB at the L level are input to the gate 15, that is, the Z dot 14. At this time, the signal V O of the node 13 is
UT is calculated to be L level and this calculated value is stored.

From time t3 to t4, when data DA is at L level and data DB is switched to H level, the second gate 12
The output vb becomes H level.

On the other hand, the first gate 11 remains in the Z-float state.

Therefore, the Z dot 14 receives the dot manual power ZA in the Z floating state and the dot input ZB at the H level. At this time, the signal V OUT of the node 13 is calculated to be H level based on the H level dot input ZH, and
This calculated value is memorized.

From time t4 to t5, data DA and control signal B switch to H level, and data DB switches to L level. As a result, the first and second gates ll,
12 are both in the Z float state. Therefore, Z dot I
4, the dot human power ZA and ZB in the Z floating state are input. Therefore, the previous time, that is, time t3 to t4
Since the signal V OUT at the node 14 at the time is at H level, this H level is applied to the node 13 at the time from t4 to t5.
Let the output signal be V OUT.

That is, even if both the first and second gates If and 12 are in the Z-float state, the output signal of the node 13 is VOUT is not set in the Z-float state, but set at H level. Therefore, the first and second
This means that the dynamic memory function of the Z dot 14, which occurs in relation to the gates 11 and 12, is taken into consideration, and this means that the calculation is in accordance with the actual operation.

In this way, in this embodiment, in the Z dot 14 having a dynamic memory function, when the output signals Va and Vb of each gate 11 and 12 are both in the Z float state (high impedance) by calculation, Since the state of the immediately preceding output signal V 0LIT is used as the output signal V 0LIT, it is possible to perform an accurate and highly accurate simulation that corresponds to the actual operation, and it is possible to improve the failure detection rate.

Moreover, the output signal V of the node 13 calculated at each time
OUT is memorized, and when the calculated output signals Va and Vb of each gate 11 and 12 are in a high impedance state, the memorized state of the output signal V OUT of the previous node 13 is set as the output signal V OUT. This simulation can be performed by only slightly modifying the program of the simulation device, and the processing time can be significantly reduced.

In this embodiment, CMOS transmission gates 11 and 12 are used as the MOS transistor gates, but the present invention is not limited to this.
It may be implemented using a MOS transistor gate other than the MOS transmission gates 11 and 12, such as a MOS transistor gate composed only of PMO8 or NM'OS transistors.

[Effects of the Invention] As described in detail above, according to the simulation method of the present invention, it is possible to perform a simulation in accordance with the actual operation in consideration of the dynamic memory function in a short processing time and in a simple manner. It has an excellent effect of improving the detection rate, etc.

FIG. 2 is an electrical circuit diagram of a semiconductor integrated circuit used to explain an embodiment of the present invention, and FIG. 3 is a time chart diagram of the semiconductor integrated circuit used to explain an embodiment of the present invention.

In the figure, 11 is the first gate, J2 is the second gate, 13 is a node, 14 is Z dot, 15 is a gate.

[Brief explanation of drawings]

Fig. 1 is a flowchart diagram for explaining the principle of the simulation method of the present invention.

Claims (1)

[Claims] 1. The output terminals of a plurality of MOS transistor gates are connected to one node, and the output signal outputted through each MOS transistor gate is appropriately selected by each gate and outputted to the node. In a semiconductor integrated circuit equipped with a selector, when an output signal having a logical value other than a high impedance state is output from at least one of the MOS transistor gates to the node, a signal value of the logical sum of the respective output signals; is set as the output signal of the node, and its signal value is stored, and when all MOS transistor gates are in a high impedance state, the previously calculated and stored signal value is sent to the node instead of the high impedance output signal. A method for simulating a semiconductor integrated circuit, characterized in that an output signal is set as an output signal. 2. The MOS transistor gate according to claim 1 is a CMO
1. A simulation method for a semiconductor integrated circuit, characterized in that it is configured with S transmission gates.