JP3107025B2 - Semiconductor integrated circuit and test method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a test method therefor, and more particularly to a semiconductor integrated circuit having a large-scale macro and a test circuit built therein and a test method therefor.

[0002]

2. Description of the Related Art With the recent increase in the scale of semiconductor integrated circuits, it has become common to incorporate analog circuits and memory circuits as one macro in a semiconductor integrated circuit.
Against the background that the macro core called “tual property” has been distributed as a business,
System LSIs have come to incorporate more complex large-scale macros. As a test method for a system LSI incorporating these large-scale macros, a test circuit is set between the large-scale macros, and these large-scale macros can be accessed from outside the system LSI without passing through other circuits or large-scale macros. Separation test of macros by directly inputting signals to the macro or by directly outputting the output signals of the large macro to be tested to the outside without passing through other circuits or large macros The method is quite popular as a known technique.

An example of an actual semiconductor integrated circuit having a large-scale macro built therein is a DRAM-
ASICs have received attention in recent years. Semicondu
ctor World, August 1997, P76-P
103 shows a test method for the above-mentioned built-in DRAM core,
Each company has announced a test method in which an input / output terminal dedicated to DRAM testing is set and a DRAM core can be directly accessed from this terminal. Referring to FIG. 4, which is a block diagram showing the basic configuration of a semiconductor integrated circuit of this type incorporating a first conventional macro separation test circuit, the first conventional semiconductor integrated circuit has two large-scale macro circuits. 8 and 9 and a test circuit 11 set between these large-scale macros 8 and 9.

Next, the operation of the first conventional semiconductor integrated circuit will be described with reference to FIG. 4. First, in a normal operation mode, the test circuit 11 is connected to an input selection terminal TT.
The level of the selection control signal T supplied from is set to '0', and the test circuit 11 selects the output signal A of the preceding large-scale macro 8 as an input in response to the level '0' of the selection control signal T, It is supplied to the next large-scale macro 9.

On the other hand, during the test, the selection control signal T
Is set to “1”, the test circuit 11 selects the test signal B supplied via the test input terminal TB as an input in response to the level “1” of the selection control signal T, and Supply to Macro 9. At this time, the test circuit 11
Of the large-scale macro 8 in front of the test circuit 11 can be unit-tested by the input terminals TI1, TI2, the output terminal TO3, and the test output terminal TTS.
Is the test input terminal TB, the input terminal TI3, and the output terminal TO
1 and TO2 enable a unit test.

The above is the basic concept of the general first conventional macro separation test.

[0007] Various proposals have been made for a method of improving this. As an example, Japanese Patent Laid-Open No.
There is a second conventional semiconductor integrated circuit described in Japanese Patent No. 2115081.

The second conventional method applying the macro separation test method
FIG. 5 is a block diagram of the semiconductor integrated circuit of FIG. 5 in which components common to those of FIG. 4 are denoted by common reference characters / numbers.
The difference from this semiconductor integrated circuit is that it further includes second and third test circuits 12 and 13, and that each of the large-scale macros 8 and 9 and each of the test circuits 11 and 12 are grouped into one large circuit. After forming the large-scale macroblocks 100 and 101, another test circuit 13 is further added between the large-scale macroblocks 100 and 101.

Thus, a connection test of wiring between large-scale macros is performed without requiring a complicated test pattern for operating a large-scale macro. FIG. 6 shows a third conventional semiconductor integrated circuit disclosed in Japanese Patent Application Laid-Open No. 4-49637, in which constituent elements common to those in FIG. The difference between the third conventional semiconductor integrated circuit and the second semiconductor integrated circuit is that large-scale macros are classified into mega macros 108 and user macros 109, and are set only on the conventional user macro 109 side. The test circuit is placed around the mega macro 108,
And the test circuit 11 are grouped as a mega macro block 100A, while the user macro 109 is also grouped with the test circuits 12, 14 as a user macro block 101A. This is intended to reduce the number of wirings between macros and to reduce wiring delays by optimizing signal wiring paths.

However, the first, second, and third above-mentioned
In the conventional semiconductor integrated circuit, the same output is obtained when a large-scale macro of the next stage is driven and when the output is directly extracted from a terminal to the outside of the LSI and a signal is detected by a detection circuit such as a comparator circuit of an LSI tester. Circuit will be used. The signal path related to the test output terminal TTS in FIGS. 4 and 5 corresponds to this.

In general, when a CMOS type LSI is considered, the required driving current of the next stage circuit inside the LSI is on the order of μA, but a 50Ω transmission line connected outside the LSI and a detection circuit thereabove are driven. To do so, a drive current on the order of mA is required.

As is apparent from the basic configuration of the first conventional semiconductor integrated circuit, in order to observe and detect the outputs of the large-scale macros 8 and 9 built in the LSI from outside the LSI, the peripheral functions of the normal functions are required. It is necessary to prepare an output circuit for driving current equivalent to a buffer, that is, a driving current on the order of mA.

The problem here is that when the LSI operates in the normal mode, in order to operate the next large-scale macro,
Although a current on the order of μA is sufficient, an output circuit that always drives a large current operates, and a through current, which is a major factor in power consumption of a CMOS circuit, flows. In other words, the conventional semiconductor integrated circuit employing the macro isolation test method has a problem that power consumption increases even when operating in the normal mode. Also, if an output circuit capable of driving such a large current drives a light-stage subsequent circuit, waveform distortion such as overshoot and undershoot is likely to occur. Such waveform distortion has few problems if the subsequent circuit is a combinational circuit. However, when the signal is a control system signal such as a clock signal or a reset signal of a sequential circuit, it causes a malfunction of the subsequent circuit. That is, the operation may be unstable with respect to the operation in the normal mode. A fourth conventional semiconductor integrated circuit and a test method thereof shown in FIG.
00B is chain-connected from the input terminal TI to the output terminal TO, and the detection target output signal of the large-scale macro to be tested is passed through the test circuit 11 in several stages and finally to the output terminal TO used in the normal mode. Let it reach and observe here.

However, the conventional fourth semiconductor integrated circuit and its test method have two problems. One is that the wiring delay increases because the signal propagates through a redundant signal path. This problem is not only a problem of the size of the delay time, but also of bus signals such as addresses and data, there is a problem that the delay time between signals of the same attribute is greatly varied. Even if the signal is output at the normal timing at the end, the signal detection side receiving the output terminal of the final stage may determine that the signal is abnormal due to the increase in the delay time or the variation in the delay time between the signals. is there.

Another problem is that the number of test circuits around other large-scale macros for relaying and the number of final terminals are larger than the number of output signals of the large-scale macro to be taken out. It is not always consistent or sufficient. In order to avoid this problem, it is conceivable to make adjustments via a multiplexing / distributing circuit other than the known test circuit 11, but this further amplifies the first problem and complicates its control. Will be.

[0016]

SUMMARY OF THE INVENTION The above-mentioned first and second prior arts are known.
The second and third semiconductor integrated circuits and the test method thereof are different in the case where the next-stage large-scale macro is driven and the case where the output is LS
Since the same output circuit is used in the case where the signal is extracted to the outside of I and the signal is detected by the external detection circuit, this output circuit requires the driving capability of the external circuit. Therefore, there is a disadvantage that the through current causes an increase in power consumption.

When the output circuit having such a large current driving capability drives a light-stage subsequent circuit, waveform distortion such as overshoot and undershoot is likely to occur. A control signal such as a clock signal or a reset signal causes a malfunction of a subsequent circuit, thereby causing a problem that the operation in the normal mode may be unstable.

The fourth conventional semiconductor circuit and the test method therefor which solve the above-mentioned drawbacks have the disadvantage that the wiring delay increases due to the propagation of the redundant signal path and that the output signal of the large-scale macro to be externally output is increased. The number of test circuits around the other large-scale macros for relaying and the number of final terminals may not always match or be sufficient with respect to the number. .

An object of the present invention is to realize an easy test by applying a macro separation test method to an LSI having a large-scale macro built therein, and at the time of operation in a normal mode, to realize a through current. An object of the present invention is to provide a semiconductor integrated circuit which suppresses an increase in power consumption and realizes a stable operation, and a test method therefor.

[0020]

According to the present invention, there is provided a semiconductor integrated circuit comprising at least one large-scale macro, an output signal of the large-scale macro in response to the supply of a test selection control signal, and a predetermined externally supplied signal. And a test circuit that outputs one of the test signals to the next-stage internal circuit and an external output terminal for testing, wherein the test circuit responds to the supply of the test selection control signal. wherein the selection function times <br/> circuit for outputting a selection signal by selecting either the output signal and the test signal of a large macro, the selection signal is connected downstream of the selecting function circuit Te
Driving capacity depends on the level of the driving capacity control signal for output.
An output buffer circuit having a variable driving capability that changes is built in, and in a normal operation in which a test device is not connected to the external output terminal, the selection signal is supplied only to the internal circuit so that the driving capability of the output buffer circuit is reduced. And a driving capability adjusting function circuit for controlling the output buffer circuit to increase the driving capability when outputting the selection signal to the test device connected to the external output terminal during a test.

According to the method for testing a semiconductor integrated circuit of the present invention, at least one large-scale macro, an output signal of the large-scale macro in response to supply of a test selection control signal, and a predetermined test signal supplied from the outside. And a selection function circuit for selecting either one of the above and outputting as a selection signal to the internal circuit of the next stage and an external output terminal for testing .
Connected to the subsequent stage to control the driving capability for the selection signal output
Variable output capacity output buffer with variable drive capacity
A method of testing a semiconductor integrated circuit and a test circuit having a driving capability adjusting function circuit having a built-in circuit, the
Execution of a separation test for outputting an output of a large-scale macro as the selection signal to a test device connected to the external output terminal
Occasionally corresponds to the output terminal under test of this large-scale macro
Run the test in a state where the control was to be increased the <br/> driving capability of the output buffer circuit of the test circuit built for
In other cases, the driving capability is reduced.
By controlling, the generation of an excessive through current is suppressed .

[0022]

FIG. 1 is a block diagram showing a test circuit 1 which characterizes a first embodiment of the present invention. Referring to FIG. 1, the test circuit 1 of this embodiment shown in FIG.
In response to the supply of the selection control signal T from the signal selection terminal TT, one of the supply of the signal A from the large-scale macro in the preceding normal operation from the input terminal TA and the test operation mode signal B from the input terminal TB A selection function unit 2 for selectively outputting one and outputting a selection signal Y; and an output corresponding to the selection signal Y in which the driving capability is adjusted in response to the supply of a control signal C for controlling the driving capability in accordance with the output destination from the control terminal TC. An adjustment function unit 3 that outputs the signal S to the output terminal TS.

Next, the operation of the test circuit 1 of the present embodiment will be described with reference to FIG. 1. First, the selection function unit 2 selects the selection control signal T like the conventional test circuit 11.
Is "0", the signal A from the large-scale macro is selected as an input. When the selection control signal T is "1", the test operation mode signal B is selected, and the selection signal Y is output. It is supplied to the drive adjustment function unit 3. The drive adjustment function unit 3 has a variable buffer for switching between a normal drive capability operation and a high drive capability operation for external drive. If the control signal C is “0”, the internal next-stage circuit is driven, and Normal driving capability operation is performed to drive the circuit.

On the other hand, when observing the output signal of the large-scale macro via the test external terminal, the load to be driven becomes larger than in the normal operation. The control is performed so as to achieve the high driving capability operation having the capability.

Next, referring to FIG. 2 which is a circuit diagram showing a specific circuit example in which the drive adjustment function unit 3 of the test circuit 1 of the present embodiment is formed by a CMOS circuit, the drive adjustment function unit 3 shown in FIG. Output circuit 31 composed of a PMOS transistor P33 and an NMOS transistor N33, a PMOS transistor P31 for normal driving capability, and a PMOS having a large gate width W, that is, a large size for high driving capability.
It includes a transistor P32, an NMOS transistor N31 for normal drive capability, an NMOS transistor N32 with a large gate width W for high drive capability, and an inverter I31 that inverts the control signal C and outputs an inverted control signal CB.

Next, referring to FIG.
First, the selection signal Y selected by the input selection unit 2 is supplied to the output circuit 31 of the drive adjustment function unit 3. First, in the case of a normal operation in which the output destination is the internal circuit of the next stage, the level of the control signal C is “0”, and “0” of the control signal C and “1” of the inverted signal CB thereof.
, A small-sized transistor P3 for normal operation
1 and N31 are turned on, and the large-sized transistors P32 and N32 are cut off. Therefore, the output circuit 31
Is supplied via the transistors P31 and N31, the current value is determined by the transistors P31 and N31, and no large through current flows during switching. Thus, unnecessary increase in power consumption during normal operation can be suppressed.

Next, in the case of a test operation in which the output destination of the drive adjustment function unit 3 is an external test circuit via the test terminal TTS, the level of the control signal C is "1". In response to "1" and its inverted signal "CB" of "0", a large-sized transistor P3 corresponding to a high driving capability operation.
2 and N32 are turned on, and the small-sized transistors P31 and N31 are cut off. Therefore, the output circuit 31
Is supplied via the transistors P32 and N32, and the current value is determined by the transistors P32 and N32, so that a sufficient load driving capability can be obtained.

A semiconductor integrated circuit according to a second embodiment of the present invention in which a test circuit 1 according to the present embodiment incorporates a large-scale macro is provided with common reference characters / numerals for components common to those in FIG. Referring to FIG. 3 which is also shown by blocks, the semiconductor integrated circuit of the present embodiment shown in FIG. The test circuit 1 of the first embodiment set between 8 and 9 is provided.

Next, the operation of this embodiment will be described with reference to FIG. 3. First, in the normal operation mode, the selection control signal T supplied from the input selection terminal TT and the supply from the control terminal TC are supplied. The level of each of the received control signals C is set to '0'. The selection function unit 2 of the test circuit 1
In response to the level “0” of the selection control signal T, the output signal A of the preceding large-scale macro 8 is selected as an input and supplied to the drive adjustment function unit 3 as the selection signal Y. Driving adjusting function unit 3 becomes normal driving capacity operation in response to the level "0" of the control signal C, and supplies an output signal S of the selection signal Y corresponding to the next stage of large-scale macro 9.

Next, when the large-scale macro 8 to be tested is to be separated and tested, the level of the selection control signal T is set to "0".
, The level of the control signal C is set to '1'.
The selection function unit 2 of the test circuit 1 selects the output signal A of the preceding large-scale macro 8 as an input in response to the level “0” of the selection control signal T, and outputs the selection signal Y. Driving adjusting function unit 3 becomes high driving performance operation in response to the level '1' of the control signal C, to the output terminal TTS for testing an output signal S of the selection signal Y corresponding high drive currents.

Next, when the large-scale macro 9 to be tested is subjected to the isolation test, the level of the selection control signal T is set to "1".
And the level of the control signal C is set to '0'.
The selection function unit 2 of the test circuit 1 selects the test operation mode signal B supplied from the input terminal TB in response to the level “1” of the selection control signal T, and outputs a selection signal Y corresponding to the signal B. . Driving adjusting function unit 3 becomes normal driving capacity operation in response to the level "0" of the control signal C, and supplies an output signal S of the selection signal Y corresponding to the next stage of large-scale macro 9.

By using the above three operation modes, a semiconductor integrated circuit having a built-in test circuit for a macro separation test can be realized without increasing power consumption in normal operation.

[0033]

As described above, according to the semiconductor integrated circuit and the test method of the present invention, when the test circuit supplies the selection signal to only the internal circuit, the drive capability is reduced and the test signal is output to the external output terminal. Has a driving capability adjusting means for controlling the driving capability to be increased, so that it is possible to suppress an excessive increase in the through current in the normal operation mode without sacrificing the easiness of the test. There is an effect that it can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a test circuit that characterizes a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a drive adjustment function unit 3 of FIG.

FIG. 3 is a block diagram showing a configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing an example of a conventional first semiconductor integrated circuit.

FIG. 5 is a block diagram showing an example of a second conventional semiconductor integrated circuit.

FIG. 6 is a block diagram illustrating an example of a conventional first semiconductor integrated circuit.

FIG. 7 is a block diagram showing an example of a second conventional semiconductor integrated circuit.

[Explanation of symbols]

1, 11, 12, 13 Test circuit 2 Selection function unit 3 Drive adjustment function unit 8, 9 Large-scale macro 31 Output circuit 100, 101, 100A, 101A, 100B Large-scale macro block 108 Mega macro 109 User macro N31 to N33, P31 ~ P33 Transistor I31 Inverter

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G01R 31/28-31/3193 H01L 21/822 H01L 27/04 H03K 19/00 H03K 19/0175

Claims (7)

(57) [Claims] An output signal of at least one large-scale macro and one of an output signal of the large-scale macro and a predetermined test signal supplied from the outside in response to supply of a test selection control signal are transmitted to a next stage. A semiconductor integrated circuit comprising: an internal circuit; and a test circuit that outputs to an external output terminal for testing, wherein the test circuit responds to the supply of the test selection control signal and outputs an output signal of the large-scale macro and the test signal. Select one of the two to output as a selection signal
A function circuit , connected to a subsequent stage of the selection function circuit, for outputting the selection signal.
The driving capability changes according to the level of the driving capability control signal.
An output buffer circuit having a variable driving capability, and reducing the driving capability of the output buffer circuit to supply the selection signal only to the internal circuit during a normal operation in which a test device is not connected to the external output terminal; A semiconductor integrated circuit comprising: a driving capability adjusting function circuit for controlling to increase the driving capability of the output buffer circuit when outputting the selection signal to the test device connected to the external output terminal during a test. . 2. The semiconductor integrated circuit according to claim 1, wherein the internal circuit is a second large-scale macro arranged next to the preceding large-scale macro that is the first large-scale macro. circuit. Wherein the driving capability adjustment function circuit, and further comprising a current capacity switching means for switching selectively the magnitude of the supply current capacity to the output buffer circuit in response to the level of the drivability control signal The semiconductor integrated circuit according to claim 1. 4. A small-sized MOS transistor having a small current capacity, one end of which is connected to a power supply and the other end of which is connected to a power supply terminal of the output buffer circuit. A large-sized MOS transistor having a large current capability connected in parallel;
The current supply capacity is switched by controlling each gate with the driving capability control signal.
3. The semiconductor integrated circuit according to item 3 . 5. An output buffer circuit comprising: a first conductivity type first MOS transistor for connecting the gates in common, receiving the selection signal, connecting the drains in common, and outputting the buffer output signal; A second M of conductivity type 2
An OS transistor; wherein the current capacity switching means has a small current capacity having a source connected to the first power supply, a drain connected to the source of the first MOS transistor, and a gate supplied with the drive capability control signal. A third MOS transistor of a first conductivity type, an inverted driving capability control signal obtained by connecting a source to a second power source, a drain to a source of the second MOS transistor, and inverting the driving capability control signal to a gate; A fourth MOS transistor of the second conductivity type having a small size, a source connected to a first power supply, a drain connected to a source of the first MOS transistor, and a gate connected to the inversion drive capability control signal. Large-sized fifth MOS transistor of the first conductivity type having a large current capacity to receive power supply, and a source connected to the second power supply Claim, characterized by comprising said sixth MOS transistor of the large size second conductivity type supplied with drain said second respectively connected said drivability control signal to the gate to the source of the MOS transistor 3 A semiconductor integrated circuit as described in the above. 6. A semiconductor integrated circuit according to claim 5, characterized in that it comprises an inverter for generating the inversion drivability control signal by inverting said drivability control signal. 7. A method for selecting at least one large-scale macro and one of an output signal of the large-scale macro and a predetermined test signal supplied from outside in response to a supply of a test selection control signal. A selection function circuit that outputs a selection signal to the next-stage internal circuit and an external output terminal for testing;
Connected to the subsequent stage of the selection function circuit for outputting the selection signal.
Variable drivability in which the drivability changes according to the drivability control
Driving capability adjustment function circuit with built-in output buffer circuit
A test method for a semiconductor integrated circuit, comprising: a test circuit having a large scale macro output to the test apparatus connected to the external output terminal as the selection signal .
During execution, the output terminal to be tested for this large macro
Of the corresponding output buffer circuit with the built-in test circuit
The test with controls to increase the driving capability
Execute, otherwise reduce the drive capacity
A test method for a semiconductor integrated circuit, characterized in that the control is performed in such a manner as to suppress generation of an excessive through current .