JP2001324544A - Flip-flop circuit for scan pass test - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve an operating speed. SOLUTION: In a normal operation mode, a control signal sc is set to '1', a control signal scn is set to '0', and a scan data receiving clocked inverter 24 is set to an off-state and separated from a node 25. Clocked inverters 23, 26b, 27 and 28b are turned on and off by control signals dc, dcn, c and cn to receive the normal data DI and to output the data at the prescribed timing. In a shift mode of a scan pass test, the control signal dc is set to '1', the control signal dcn is set to '0', and the data receiving clocked inverter 23 is set to an off-state and separated from the node 25. The inverters 24, 26b, 27 and 28b are turned on and off by the control signals sc, scn, c and cn to receive the scan data SI and to output the data at the prescribed timing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a flip-flop (FF) circuit for a scan path test, which is one of circuit components used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art FIGS. 2A and 2B are configuration diagrams showing an example of a conventional semiconductor integrated circuit. The semiconductor integrated circuit shown in FIG. 2A has FF circuits 1-11 to 1-1n that take in a plurality of data SI1 to SIn.
A combination circuit 2-1 combining various logic circuits and the like is connected. On the output side of the combinational circuit 2-1, via a plurality of FF circuits 1-2 to 1-2 n for taking in data,
The next-stage combinational circuit 2-2 is connected. The output side of the combinational circuit 2-2 is connected with a plurality of data taking-in FF circuits 1-31 to 1-3n.
A plurality of data Q1 to Qn are output from -31 to 1-3n. FF circuits 1-11 to 1-1n,
1-2-1 to 1-2n, 1-31 to 1-3n and combinational circuits 2-1 and 2-2 are provided with an arbitrary number of stages according to the configuration of the semiconductor integrated circuit.

In such a semiconductor integrated circuit, for example,
When a plurality of data SI1 to SIn are supplied, these data SI1 to SIn are taken into the FF circuits 1-11 to 1-1n and sent to the combinational circuit 2-1 at a predetermined timing. The combinational circuit 2-1 performs a predetermined logical operation and outputs the logical result. The output logical result is
The FF circuits 1-2-1 to 1-2n at the next stage take in the signals and send them to the combination circuit 2-2 at the next stage at a predetermined timing. The combinational circuit 2-2 performs a predetermined logical operation,
This logical result is output. The output logic result is taken into a plurality of FF circuits 1-3-1 to 1-3n at the next stage, and a plurality of data Q1 to Qn are output at a predetermined timing.

In this type of semiconductor integrated circuit, when performing a logical operation test, data SI1 to SIn of a predetermined test pattern are supplied. The supplied data SI1
SIn is taken into the FF circuits 1-11 to 1-1n,
Combination circuit 2-1, a plurality of FF circuits 1-2-1 to 1-2
n, combinational circuit 2-2, and a plurality of FF circuits 1-31 to 31-31
A predetermined operation is performed in 1-3n. The operation result is output as a plurality of data Q1 to Qn. By comparing the data Q1 to Qn with expected values, a test can be performed as to whether or not the logic operation of the semiconductor integrated circuit has been performed correctly.

In such a test method, for example, the values of the plurality of FF circuits 1-2-1 to 1-2n are determined by the preceding combination circuit 2-1. In order to test whether or not each circuit portion operates normally, a huge amount of test pattern data SI1 to SIn in consideration of a combination of all circuit portions constituting the semiconductor integrated circuit is required. Therefore, to facilitate the test, a scan path test method as shown in FIG. 2B has been proposed.

In the semiconductor integrated circuit shown in FIG.
F circuits 1-11 to 1-1n, 1-21 to 1-2n, 1-
, 31-1 to 3n, ... are FF circuits 1A-11 to 1A-1n, 1A-21 to 1A-2n, 1 for scan path test.
, And all of these FF circuits 1A-11 to 1A-1n, 1A-21 to 1A-
2n, 1A-31 to 1A-3n,... Are connected in cascade.

FIG. 3 shows the scan path test FF circuits 1A-11 to 1A-1n and 1A-21 shown in FIG.
1A to 2A, 1A-31 to 1A-3n,... This scan path test FF circuit 1
A has a data input terminal 11 for inputting data DI and a scan data input terminal 12 for inputting scan data SI, and a selector 13 having two inputs and one output is connected to these terminals 11 and 12. The selector 13 receives the input data DI in response to the selector control signal SEL.
Alternatively, one of the scan data SI is selected and output as data D, and a delay type F
The data input terminal 14a of the F (hereinafter referred to as "D-FF") 14 is connected. The D-FF 14 is a circuit that fetches data D from the data input terminal 14a and outputs data Q delayed from the data output terminal 14c at a predetermined timing in synchronization with the clock signal CK input to the clock input terminal 14b. .

In the semiconductor integrated circuit of FIG. 2B, by switching the selector control signal SEL, during normal operation, normal data SI1 to SIn are transferred to the FF circuit 1A-.
The scan data SI is taken into the FF circuit 1A-11 at the time of the scan path test. The scan data SI captured by the FF circuits 1A-11 are the FF circuits 1A-12 to 1A-1n and 1A-21.
-1A-2n, 1A-31-1A-3n,... As a result, the scan data SI supplied from the outside is directly transferred to the FF circuits 1A-11 to 1A-1n,
1A-21 to 1A-2n, 1A-31 to 1A-3n, ...
Therefore, it is possible to test whether or not each circuit portion in the semiconductor integrated circuit operates normally by using a small number of test pattern combinations.

[0009]

However, in the conventional scan path test FF circuit 1A, the DF circuit is required to select the input of the data DI or the scan data SI.
Since the selector 13 is provided on the input side of F14,
The setup time of the circuit 1A increases, and the FF circuit 1
There is a problem that the maximum operation speed in the semiconductor integrated circuit of FIG. SUMMARY OF THE INVENTION It is an object of the present invention to solve the problems of the prior art and to provide a scan path test FF circuit capable of high-speed operation.

[0010]

According to a first aspect of the present invention, there is provided a scan path test FF circuit having first and second potentials having different levels of first and second potentials. A data fetching means for fetching normal data in the normal operation mode in response to the transition of the control signal and outputting the data to the node at a predetermined timing; and a second control signal having first and second potentials having different levels. A scan data acquisition means for acquiring scan data in a shift mode of a scan path test in response to a transition and outputting the scan data to the node at a predetermined timing;
And latch means for latching data on the node in response to a transition of a third control signal having a second potential and outputting the data at a predetermined timing.

By adopting such a configuration, in the normal operation mode, normal data is fetched by the data fetching means in response to the transition of the first control signal, and is output to the node at a predetermined timing. The data output to the node is latched by the latch means in response to the transition of the third control signal, and is output at a predetermined timing. In shift mode of scan path test,
In response to the transition of the second control signal, the scan data is fetched by the scan data fetching means and output to the node at a predetermined timing. The scan data output to the node is latched by the latch means in response to the transition of the third control signal, and is output at a predetermined timing.

According to a second aspect, in the scan path test FF circuit according to the first aspect, the latch means latches data on the node in response to a transition of the third control signal and performs a predetermined operation. A first latch circuit that outputs at a timing; a transfer circuit that transfers output data of the first latch circuit in response to a transition of the third control signal; and a transfer circuit that responds to a transition of the third control signal. A second latch circuit for latching the output data of the transfer circuit and outputting the latched data at a predetermined timing. Thereby, the data on the node is latched by the first latch circuit in response to the transition of the first control signal, and the latched data is transferred by the transfer circuit and latched by the second latch circuit. Thereafter, it is output at a predetermined timing.

According to a third aspect of the present invention, in the scan path test FF circuit according to the first or second aspect, the output terminal of the scan data capturing means and the node are connected or disconnected by exchanging a metal mask. Are connected by metal wiring that can be used. This makes it possible to easily connect or disconnect the metal wiring by replacing the metal mask. When a desired operation speed cannot be obtained when this scan path test FF circuit is incorporated in a semiconductor integrated circuit, the operation load can be improved by reducing the output load of the data capturing means by disconnecting the metal wiring. .

According to a fourth aspect of the present invention, in the scan path test FF circuit according to the first, second or third aspect, the data capturing means and the scan data capturing means are each constituted by a clocked inverter. Thereby, either the normal data or the scan data can be easily taken in by the first and second control signals.

[0015]

(First Embodiment) FIG. 1 is a configuration diagram of a master-slave type scan path test FF circuit according to a first embodiment of the present invention. This master-slave scan path test FF circuit has a data input terminal 21 for inputting normal data DI and a scan data input terminal 22 for inputting scan data SI. The data input terminal 21 is connected to a data capturing unit (for example, a clocked inverter) 23, and the scan data input terminal 22 is connected to a scan data capturing unit (for example, a clocked inverter) 24. The clocked inverter 23 for taking in data is controlled by complementary first control signals dc and dcn, and is turned on when the control signal dc has a logical value “0” (the control signal dcn has a logical value “1”). And the input data DI is inverted and output, and the control signal dc becomes "1".
This is a circuit that is turned off when the control signal dcn is “0”. The clocked inverter 24 for taking in scan data is controlled by complementary second control signals sc and scn, and this control signal sc is set to “0” (control signal s
This circuit is turned on when cn is "1", inverts and outputs the input scan data SI, and is turned off when the control signal sc is "1" (control signal scn is "0").

The output terminals of the clocked inverters 23 and 24 are connected to latch means via a node 25. This latch means provides a complementary third control signal c,
This is a circuit that latches the data on the node 25 in response to the transition of cn and outputs the data to the data output terminal 29 at a predetermined timing.
Clocked inverter) 27, and second latch circuit 2
8.

The first latch circuit 26 is a circuit that latches data on the node 25 in response to transitions of the complementary third control signals c and cn and outputs the data at a predetermined timing. It comprises a connected inverter 26a and a clocked inverter 26b connected between the input terminal and the output terminal of the inverter 26a.
A second latch circuit 28 is connected to an output terminal of the inverter 26a via a clocked inverter 27 for transfer. The second latch circuit 28 is a circuit that latches output data of the clocked inverter 27 in response to transition of the third control signals c and cn and outputs the latched data to the data output terminal 29 at a predetermined timing. An inverter 28a is connected to the output terminal of the inverter 27, and a clocked inverter 28b is connected between the output terminal and the input terminal of the inverter 28a.

FIG. 4 shows the control signals dc, dcn, s of FIG.
FIG. 3 is a configuration diagram illustrating an example of a control signal generation circuit for generating c, scn, c, and cn. This control signal generation circuit inverts the clock signal CLK to generate a third control signal cn.
And a third control signal dcn by inputting the clock signal CLK and the scan signal SCAN.
And a scan signal S
An inverter 33 for inverting CAN and a clock signal CL
And a two-input NOR gate 34 that inputs the output signal of the inverter 33 and outputs the second control signal scn. The output terminal of the inverter 31 has a control signal cn
35 that inverts and outputs a third control signal c
Is connected. The output terminal of the NOR gate 32
An inverter 36 that inverts the control signal dcn and outputs a first control signal dc is connected. NOR gate 34
Is connected to an inverter 37 that inverts the control signal scn and outputs a second control signal sc.

In this control signal generation circuit, when the clock signal CLK and the scan signal SCAN are input, the clock signal CLK is inverted by the inverter 31 to output the control signal cn, and the control signal cn
Are inverted by the inverter 35 to output the control signal c. When the scan signal SCAN is “0”, the NOR gate 32 is turned on, and the clock signal CLK is
The control signal dcn is output after being inverted by the OR gate 32, and the control signal dc is output after being inverted by the inverter 36. At this time, since scan signal SCAN is inverted by inverter 33, NOR
Gate 34 is turned off. When the scan signal SCAN is "1", the NOR gate 32 is turned off, whereas the NOR gate 34 is turned on. When the NOR gate 34 is turned on, the clock signal CLK becomes N
The control signal scn is output after being inverted by the OR gate 34, and the control signal sc is output after being inverted by the inverter 37.

FIG. 5 shows the clocked inverter 23 of FIG.
FIG. 3 is a configuration diagram illustrating an example of the configuration. The clocked inverter 23 has an inverter 41 for inverting the control signal dc.
The gate of an S transistor (hereinafter referred to as “NMOS”) 42 is connected. The power supply potential VCC is connected to the drain of the NMOS 42. A P-channel MOS transistor (hereinafter referred to as “PMOS”) 43 is connected between the source of the NMOS 42 and the node 25, and the gate of the PMOS 43 is connected to the data input terminal 21. 2 between the node 25 and the ground GND
NMOS transistors 44 and 45 are connected in series. NMO
The data input terminal 21 is connected to the gate of S44. The control signal dcn is input to the gate of the NMOS 45.

In the clocked inverter 23, when the input control signal dc is "0" (the control signal dcn is "1"), the control signal dc is inverted by the inverter 41 to become "1", and the NMOS 42 is turned on. It turns on. At this time, since the control signal dcn is “1”, the NMOS
45 is also turned on. Thereby, the data input terminal 2
When the data DI input to "1" is "0", the PMOS
43 is turned on, the NMOS 44 is turned off, and the node 25 becomes “1”. When the data DI is “1”,
The PMOS 43 is turned off, the NMOS 44 is turned on, and the node 25 becomes “0”.

The other clocked inverters 24, 2 in FIG.
6b, 27, and 28b have the same configuration as in FIG. FIG.
(A) and (b) are scan path test FFs shown in FIG.
4A and 4B are timing charts for explaining the operation of the circuit. FIG. 4A is a timing chart in a normal operation mode, and FIG. 4B is a timing chart in a shift mode of a scan path test. Hereinafter, FIG.
The operation (A) in the normal operation mode and the operation (B) in the shift mode of the scan path test will be described with reference to (a) and (b).

(A) Operation in Normal Operation Mode (FIG. 6)
(A)) The control signal sc is set to "1" and the control signal scn is set to "0". As a result, clocked inverter 24 is turned off, and this clocked inverter 24
It becomes a state disconnected from. When the control signals dc, c fall to “0” and the control signals dcn, cn rise to “1”, the clocked inverters 23, 2
8b is turned on, and the clocked inverters 26b and 27 are turned off. As a result, the data DI supplied to the data input terminal 21 is taken into the clocked inverter 23. Next, when the control signals dc and c rise to "1" and the control signals dcn and cn fall to "0", the clocked inverters 23 and 28b are turned off and the clocked inverters 26b and 27 are turned on. Become. Thus, the fetched data DI is output from the data output terminal 29 in the form of data Q. Therefore, F in FIG.
The F circuit operates as a normal master-slave FF circuit.

(B) Operation in Shift Mode of Scan Path Test (FIG. 6 (b)) When the control signal dc is set to "1" and the control signal dcn is set to "0", the clocked inverter 23 is turned off. Thus, the clocked inverter 23 is disconnected from the node 25. When the control signals sc and c fall to "0" and the control signals scn and cn rise to "1", the clocked inverters 24 and 28b are turned on and the clocked inverters 26b and 27 are turned off. As a result, the scan data SI supplied to the scan data input terminal 22 is
It is taken in. Next, when the control signals sc and c rise to "1" and the control signals scn and cn fall to "0", the clocked inverters 24 and 28b are turned off and the clocked inverters 26b and 27 are turned on. Become. As a result, the acquired scan data SI becomes
The data is output from the data output terminal 29 in the form of data Q. Therefore, when a semiconductor integrated circuit as shown in FIG. 2B is configured using the scan path test FF circuit of FIG. 1, a scan path test of this semiconductor integrated circuit can be performed.

The first embodiment has the following effects. Conventional FF for scan path test as shown in FIG.
Since the selector 13 in the circuit is removed and one clocked inverter 24 is connected to the scan data input terminal 22, the time required for data propagation by the amount of the selector 13 (ie, the data propagation delay time when passing through the selector 13) ) Can be reduced, and the same operation as that of the conventional scan path test FF circuit as shown in FIG. 3 can be guaranteed. Therefore, if a semiconductor integrated circuit as shown in FIG. 2B is configured using the scan path test FF circuit of the present embodiment, the setup time of the scan path test FF circuit does not increase, and the semiconductor integrated circuit Operation speed can be increased.

(Second Embodiment) FIG. 7 shows a second embodiment of the present invention.
FIG. 2 is a configuration diagram of a scan path test FF circuit according to the first embodiment, in which components common to those in FIG. 1 according to the first embodiment are denoted by common reference numerals. In the scan path test FF circuit according to the second embodiment, the metal wiring 30 that can be connected or disconnected by exchanging a metal mask connects the output terminal of the clocked inverter 24 for taking in scan data and the node 25. Connected. Other configurations are the same as those of the first embodiment. When the output terminal of the clocked inverter 24 and the node 25 are connected by the metal wiring 30, the circuit is the same as that of the first embodiment shown in FIG. 1, and performs the same operation as that of the first embodiment. On the other hand, when the metal wiring 30 is removed by exchanging the metal mask, the same operation as that of a normal master-slave FF circuit is performed.

The second embodiment has the following effects. The metal wiring 30 can be easily connected or disconnected by exchanging the metal mask. Using the scan path test FF circuit, a semiconductor integrated circuit as shown in FIG. 2B is designed, and as a result of measuring the operation speed of the semiconductor integrated circuit, if a desired operation speed cannot be obtained, a metal mask is used. The metal wiring 30 is cut off by replacing the wiring, and the load on the wiring capacitance when the clocked inverter 24 is viewed from the node 25 is reduced. As a result, the operation speed can be increased, so that it cannot be used for a scan path test, but can be used as a normal semiconductor integrated circuit.

(Modifications) The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications (a) to (c). (A) The data fetching means and the scan data fetching means are constituted by the clocked inverters 23 and 24, respectively, but may be constituted by other circuits. For example, a transfer gate having a configuration in which transistors such as a field effect transistor (FET) are connected in parallel may be used. (B) The first and second latch circuits 26 and 28 and the clocked inverter 27 for the transfer circuit may be constituted by another circuit such as a transfer gate. Node 25
Latch means connected to the first and second latch circuits 2
Instead of the clocked inverters 6 and 28 and the clocked inverter 27 for the transfer circuit, another FF may be used. (C) The metal wiring 30 is configured such that connection or disconnection can be performed by replacing the metal mask. However, instead of such replacement of the metal mask, the connection or disconnection of the metal wiring 30 can be performed by another method. It is also possible to

[0029]

As described above in detail, according to the first and second aspects of the present invention, the selector provided on the input side of the conventional data capturing means is removed, and the scan data capturing means is replaced with the data capturing means. Since they are connected in parallel, the time required for data propagation can be reduced by the amount of the selector as in the related art. Thus, it is possible to prevent an increase in setup time due to the provision of the conventional selector. Therefore, when a semiconductor integrated circuit is configured using the scan path test FF circuit of the present invention, the speed of the semiconductor integrated circuit can be increased.

According to the third aspect, since the metal wiring is used to connect the output terminal of the scan data capturing means and the node, the metal wiring can be easily connected or disconnected by exchanging the metal mask. it can. For this reason, for example, a semiconductor integrated circuit is designed using the scan path test FF circuit of the present invention, and the operation speed of the semiconductor integrated circuit is measured. The load on the connected wiring capacitance can be reduced, and the operation speed can be improved. As a result, the scan path test of the semiconductor integrated circuit cannot be performed, but the operation and effect of a normal semiconductor integrated circuit can be expected. According to the fourth aspect, since the data fetching means and the scan data fetching means are each constituted by a clocked inverter, data fetching can be performed easily and accurately.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a scan path test FF circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram illustrating an example of a conventional semiconductor integrated circuit.

FIG. 3 is a configuration diagram showing an example of a conventional scan path test FF circuit 1A in FIG. 2B.

FIG. 4 is a configuration diagram illustrating an example of a control signal generation circuit for generating the control signal of FIG. 1;

FIG. 5 is a configuration diagram illustrating an example of a clocked inverter 23 in FIG. 1;

FIG. 6 is a timing chart illustrating the operation of the scan path test FF circuit of FIG. 1;

FIG. 7 is a configuration diagram of a scan path test FF circuit according to a second embodiment of the present invention.

[Explanation of symbols]

23 Clocked Inverter for Data Capture 24 Clocked Inverter for Scan Data Capture 25 Node 26 First Latch Circuit 27 Clocked Inverter for Transfer 28 Second Latch Circuit 30 Metal Wiring

Claims (4)

[Claims] 1. A data fetch means for fetching normal data in a normal operation mode in response to a transition of a first control signal having first and second potentials having different levels, and outputting the normal data to a node at a predetermined timing. Scan data capture means for capturing scan data in a shift mode of a scan path test in response to transition of a second control signal having first and second potentials having different levels and outputting the scan data to the node at a predetermined timing And latch means for latching data on the node in response to a transition of a third control signal having first and second potentials having different levels and outputting the data at a predetermined timing. Scan path test flip-flop circuit. 2. A latch circuit, comprising: a first latch circuit that latches data on the node in response to a transition of the third control signal and outputs the data at a predetermined timing; and a third control signal. And a transfer circuit for transferring output data of the first latch circuit in response to the transition of the third control signal, and latching output data of the transfer circuit in response to a transition of the third control signal and outputting the latched data at a predetermined timing Second
2. The flip-flop circuit for scan path test according to claim 1, wherein the latch circuit comprises: 3. An output terminal of the scan data capturing means and the node are connected by a metal wiring which can be connected or disconnected by exchanging a metal mask. Flip-flop circuit for scan path test. 4. The flip-flop circuit for a scan path test according to claim 1, wherein said data fetch means and said scan data fetch means are each constituted by a clocked inverter.