JP2009222558A - Flip-flop circuit for scanning - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a flip-flop circuit for scanning operated at higher speed by suppressing increase of a delay time, and to provide an integrated circuit scanning method which uses the flip-flop circuit for scanning. <P>SOLUTION: Only one transfer circuit is arranged between an inverter circuit for data signal input and an inverter circuit, in a master latch circuit part for inputting a signal from the inverter circuit for data signal input. One more transfer circuit forming a pair with the transfer circuit and operated added exclusively, rather than the master latch circuit part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a flip-flop circuit or a latch circuit for scanning, a shift register using these circuits, an integrated circuit using the shift register, and a scanning method in the integrated circuit, and more particularly to a one-phase clock. The present invention relates to a flip-flop circuit or a latch circuit for scanning by a method, a shift register using these circuits, an integrated circuit using the shift register, and a scanning method in the integrated circuit.

  In recent years, the operating frequency of computer systems has increased with the improvement in performance. Therefore, it is necessary to reduce the circuit delay time in the LSI used in the system. It must be avoided that the circuit delay time increases by adding a test circuit.

  FIG. 3 is a circuit diagram of a scan latch circuit using a one-phase clock method according to the related art. In the latch circuit shown in this circuit diagram, a transfer circuit is additionally connected in front of the master latch circuit to switch between normal data and scan data.

  First, the circuit diagram of FIG. 3 will be described. The latch circuit includes a data signal input circuit unit 1, a scan signal input circuit unit 2, a master latch circuit unit 3, a slave latch circuit unit 4, a clock signal shift signal input circuit unit 5, and a data output circuit unit 6. And a scan output circuit unit 7.

  The data signal input circuit unit 1 includes a data signal input unit (DAT) 11, an inverter circuit (INV4) 12, and a transfer circuit (TG1) 13. The transfer circuit (TG1) 13 includes an SFB signal input unit 131 and an SFT signal input unit 132.

  The scan signal input circuit unit 2 includes a scan signal input unit (SIN) 21, an inverter circuit 22 (INV5), and a transfer circuit (TG2) 23. The transfer circuit (TG2) 2 includes an SFT signal input unit 233 and an SFB signal input unit 234.

  The master latch circuit unit (LLT) 3 includes a transfer circuit (TG4) 31, an inverter circuit (INV6) 32, an inverter circuit (INV7) 34, and a transfer circuit (TG3) 35. The transfer circuit (TG4) 31 includes a CKB signal input unit 311 and a CKT signal input unit 312. The transfer circuit (TG3) 35 includes a CKT signal input unit 351 and a CKB signal input unit 352.

  The slave latch circuit unit (LHT) 4 includes a transfer circuit (TG5) 41, an inverter circuit (INV9) 42, an inverter circuit (INV10) 44, and a transfer circuit (TG6) 43. The transfer circuit (TG5) 41 includes a CKT signal input unit 411 and a CKB signal input unit 412. The transfer circuit (TG6) 43 includes a CKB signal input unit 431 and a CKT signal input unit 432.

  The clock signal shift signal input circuit unit 5 includes a clock signal input unit (CLK) 51, an inverter circuit (INV1) 53, a CKB signal output unit (CKB) 574, an inverter circuit (INV2) 54, and a CKT signal output unit. (CKT) 573, a shift signal input unit (SFT) 52, an SFT signal output unit (SFT) 575, an inverter circuit (INV3) 55, and an SFB signal output unit (SFB) 576 are provided.

  The data output circuit unit 6 includes an inverter circuit (INV8) 61 and a data output unit (OUT) 62.

  The scan output circuit unit 7 includes an inverter circuit (INV11) 71 and a scan output unit (SOT) 72.

Next, the connection relationship between the various components will be described.
In the data signal input circuit unit 1, the data signal input unit (DAT) 11 is connected to the input of the inverter circuit (INV4). The output of the inverter circuit (INV4) is connected to the transfer circuit (TG1) 13. On the other hand, the transfer circuit (TG1) 13 is connected to the transfer circuit (TG4) 31. The SFB signal input unit 131 is connected to the SFB signal output unit 576. The SFT signal input unit 132 is connected to the SFT signal output unit 575.

  In the scan signal input circuit unit 2, the scan signal input unit (SIN) 21 is connected to the input of the inverter circuit (INV 5) 53. The output of the inverter circuit (INV5) 53 is connected to the transfer circuit (TG2) 23. On the other hand, the transfer circuit (TG2) 23 is connected to the transfer circuit (TG4) 31. The SFT signal input unit 233 is connected to the SFT signal output unit 575. The SFB signal input unit 234 is connected to the SFB signal output unit 576.

  In the master latch circuit unit (LLT) 3, the transfer circuit (TG 4) 31 is connected to the input of the inverter circuit (INV 6) 32, the transfer circuit (TG 3) 35, and the input of the inverter circuit (INV 6) 61. . The output of the inverter circuit (INV6) 32 is connected to the input of the inverter circuit (INV7) 34 and the transfer circuit (TG5) 41. The output of the inverter circuit (INV7) 34 is connected to the transfer circuit (TG3) 35. On the other hand, the transfer circuit (TG3) 35 is connected to the transfer circuit (TG4) 31, the input of the inverter circuit (INV6) 32, and the input of the inverter circuit (INV8) 61. The two CKB signal input units 311 and 352 are connected to the CKB signal output unit 574. The two CKT signal input units 312 and 351 are connected to the CKT signal output unit 573.

  In the slave latch circuit unit (LHT) 4, the transfer circuit (TG 5) 41 is connected to the input of the inverter circuit (INV 9) 32 and the transfer circuit (TG 6) 43. The output of the inverter circuit (INV9) 42 is connected to the input of the inverter circuit (INV10) 44 and the input of the inverter circuit (INV11) 71. The output of the inverter circuit (INV10) 44 is connected to the transfer circuit (TG6) 43. The two CKT signal input units 411 and 432 are connected to the CKT signal output unit 573. The two CKB signal input units 412 and 431 are connected to the CKB signal output unit 574.

In the clock signal shift signal input circuit unit 5, the clock signal input unit (CLK) 51 is connected to the input of the inverter circuit (INV 1) 53. The output of the inverter circuit (INV1) 53 is connected to the CKB signal output unit 574 and the input of the inverter circuit (INV2) 54. The output of the inverter circuit (INV2) 54 is connected to the CKT signal output unit 573.
The shift signal input unit (SFT) 52 is connected to the SFT signal output unit (SFT) 575 and the input of the inverter circuit (INV3) 55. An output of the inverter circuit (INV3) 55 is connected to an SFB signal output unit (SFB) 576.

  In the data output circuit unit 6, the output of the inverter circuit (INV 8) 61 is connected to the data output unit (OUT) 62.

  In the scan output circuit unit 7, the output of the inverter circuit (INV 11) 71 is connected to the scan output unit (SOT) 72.

Next, the operation of the scan latch circuit in this circuit diagram will be described.
In the clock signal shift signal input circuit unit 5, the inverter circuit (INV1) 53 receives a CLK (clock) signal and generates and outputs a CKB signal. The inverter circuit (INV2) 54 receives the CKB signal and generates and outputs a CKT signal. The inverter circuit (INV3) 55 receives the SFT (shift) signal and generates and outputs the SFB signal.

  In the data signal input circuit unit 1, the inverter circuit (INV4) 12 receives the DAT signal and generates and outputs a DTB signal. The transfer circuit (TG1) 13 receives the SFB signal, and generates and outputs the W05 signal by passing the DTB signal when the condition of SFB = 1 is satisfied.

  In the scan signal input circuit unit 2, the inverter circuit (INV5) 22 receives the SIN signal and generates and outputs the SIB signal. The transfer circuit (TG2) receives the SIB signal, and generates and outputs the W05 signal by passing the SIB signal when the condition of SFT = 1 is satisfied.

  The transfer circuit (TG1) 13 and the transfer circuit (TG2) 23 are controlled by SFB and SFT which are exclusive signals. Therefore, since both transfer circuits 13 and 23 operate exclusively with each other, the DTB signal and the SIB signal do not compete as the W05 signal.

  In the master latch circuit unit (LLT) 3, the transfer circuit (TG4) 31 receives the W05 signal and, when the condition of CKB = 1 is satisfied, passes the W05 signal and generates and outputs the LM signal. The inverter circuit (INV6) 32 receives the LM signal and generates and outputs the W02 signal. The inverter circuit (INV7) 34 receives the W02 signal and generates and outputs the W01 signal. The transfer circuit (TG3) 35 receives the W01 signal and, when the condition of CKT = 1 is satisfied, passes the W01 signal and generates and outputs an LM signal. The transfer circuit (TG4) 31 and the transfer circuit (TG3) 35 are controlled by CKB and CKT which are exclusive signals. Therefore, since both transfer circuits 31 and 35 operate exclusively with each other, the W05 signal and the W01 signal do not compete as the LM signal.

  In the data output circuit unit 6, the inverter circuit (INV8) 61 receives the LM signal and generates and outputs the output signal of the data output unit (OUT) 62.

  In the slave latch circuit unit (LHT) 4, the transfer circuit (TG5) 41 receives the W02 signal and passes the W02 signal to generate the LS signal when the condition of CKT = 1 is satisfied. The inverter circuit (INV9) 42 receives the LS signal and generates and outputs the W12 signal. The inverter circuit (INV10) 44 receives the W12 signal and generates and outputs the W11 signal. The transfer circuit (TG6) 43 receives the W11 signal and, when the condition of CKB = 1 is satisfied, passes the W11 signal and generates and outputs the LS signal. The transfer circuit (TG5) 41 and the transfer circuit (TG6) 43 are controlled by the CKB signal and the CKT signal which are exclusive signals. Therefore, since both transfer circuits 41 and 43 operate exclusively with each other, the W02 signal and the W11 signal do not compete as the LS signal.

  In the scan output circuit unit 7, an inverter circuit (INV11) 71 receives the W12 signal and generates and outputs an SOT output signal.

  FIG. 10 is a time chart for explaining the operation of the scan latch circuit described in FIG. In this time chart, the horizontal axis represents the passage of time, and the vertical axis represents the binary value in each signal.

  In this description, a timing value is added by 1 for each of Low and High of the CLK signal.

  The SFT signal, DAT signal, and SIN signal are input signals. In this description, the timing at which these input signals change is determined as follows. That is, the SFT signal changes from “0 → 1” at timing 4. The DAT signal changes from “0 → 1” at timing 3 and changes from “1 → 0” at timing 5. The SIN signal changes from “0 → 1” at timing 7.

  In the data signal input circuit unit 1, the DTB signal delays the DAT signal by the delay of the inverter circuit (INV 4) 12. Similarly, in the scan signal input circuit section 2, the SIB signal also delays the SIN signal by the delay of the inverter circuit (INV 5) 22.

  In the clock signal shift signal input circuit unit 5, the SFT signal changes from “0 → 1” at timing 4.

  In the data signal input circuit unit 1, at timing 1 and timing 3, since SFT = 0, the DTB signal is selected and set as the W05 signal. Since the DTB signal value at timing 1 is “1”, “1” is set as the W05 signal value. Since the DTB signal value at timing 3 is “0”, “0” is set as the W05 signal value.

  In the scan signal input circuit 2, SFT = 1 at timing 5 and timing 7, so the SIB signal is selected and set as the W05 signal. Since the SIB signal value at timing 5 is “1”, “1” is set as the W05 signal value. Since the SIB signal value at timing 7 is “0”, “0” is set as the W05 signal value.

  In the master latch circuit unit (LLT) 3, when CLK = 1, the W05 signal is set as the LM signal. Therefore, as the LM signal, the DTB signal “1” at timing 1, the DTB signal “0” at timing 3, the SIB signal “1” at timing 5, and the SIB signal “0” at timing 7, Set each one. At timing 2, timing 4, timing 6, and timing 8, CLK = 1, so the W01 signal is set as the LM signal.

  When CLK = 0, either the DTB signal or the SIB signal is selected and set as the LM signal according to the state of the SFT signal.

  Since the LM signal is set at a timing when the selected signal is changed, the LM signal is changed at an arbitrary timing between clock edges, not a signal change synchronized with the clock edge.

  In the data output circuit unit 6, a signal delayed by the delay of the inverter circuit (INV8) 61 is output as the OUT signal.

  In the slave latch circuit section (LHT) 4, when CKT = 1, the LM signal is set as the LS signal. Since the LM signal when CKT = 1 is a signal determined to be Low or High, the LS signal is a signal change determined to be Low or High in synchronization with the clock edge.

  In the scan output circuit unit 7, a signal delayed by the delay of the inverter circuit (INV 11) 71 is output as the SOT signal.

  FIG. 6 is a circuit diagram of a scan flip-flop circuit according to the related art. This scan flip-flop circuit is equivalent to the scan latch circuit described with reference to FIG. 3 with the scan output circuit section 7 removed and the data output circuit section 6 moved thereto. That is, the scan output signal (SOT) in FIG. 3 is used as the data output signal (OUT) and the scan output signal (SOT). The other parts in the circuit diagram of FIG. 6 are the same as those in FIG.

  However, the scan latch circuit of the related art has the following problems. In other words, two stages of transfer circuits exist continuously in the path from the data signal input unit (DAT) 11 to the LM of the master latch circuit unit (LLT) 3. For this reason, the signal attenuation is large and the delay is increased.

In relation to the above, Patent Document 1 (Japanese Patent No. 3587248) discloses an invention related to a scan flip-flop circuit.
The scan flip-flop circuit of the invention of Patent Document 1 is a master-slave type having a master latch circuit portion and a slave latch circuit portion for temporarily holding an input signal, which is used in a test of a semiconductor integrated circuit device. The scan flip-flop circuit includes a first scan control unit, a clock control unit, and a second scan control unit. Here, the first scan control unit receives the output signal of the master latch circuit unit and outputs it in synchronization with a scan clock which is a test clock during the test. The clock control unit receives the output signal of the first scan control unit and outputs it to the slave latch circuit unit in synchronization with a predetermined clock during normal operation. The second scan control unit has an input connected to the output of the first scan control unit, and outputs a scan-out signal corresponding to the scan-in signal, which is an input signal for the test, in synchronization with the scan clock during the test. Is.

  The scan flip-flop circuit of the invention of Patent Document 1 relates to the invention of a two-phase clock type scan circuit. The amount of hardware of the scan circuit is 11 inverter circuits and 8 transfer circuits, which corresponds to a total of 38 transistors. In this scan circuit, the data held in the master latch circuit is output via two inverter circuits when the transfer circuit is opened by clock transition. At this time, the driving force from the inverter circuit located in the preceding stage is further reduced by another transfer circuit in the preceding stage of the transfer circuit. Accordingly, the delay from clock signal deviation to data output increases.

Patent Document 2 (Japanese Patent No. 3535855) discloses an invention relating to a scan flip-flop circuit.
The scan flip-flop circuit of the invention of Patent Document 2 has a normal operation function and a scan test operation function. Here, the normal operation function is for operating as a normal flip-flop circuit. A scan-in signal, which is a test pattern signal, is used as a data input, and operates as a flip-flop circuit by a scan clock, which is a test clock. The scan flip-flop circuit includes a master latch circuit, a slave latch circuit, and a clock circuit. Here, the master latch circuit temporarily holds input data in synchronization with a predetermined clock during normal operation, and temporarily holds a scan-in signal in synchronization with the first scan clock during scan test operation. It is. The slave latch circuit outputs a signal held by the master latch circuit in a normal operation in synchronization with the clock, and outputs a signal held in the master latch circuit in a scan test operation in synchronization with the second scan clock. It is. The clock circuit synchronizes the master latch circuit and the slave latch circuit with a positive flip-flop circuit that outputs data in synchronization with the rising edge of the clock or with the falling edge of the clock in accordance with the first switching signal input from the outside. Generating a first control signal for setting to either one of the negative flip-flop circuits for outputting data, and setting the master latch circuit and the slave latch circuit in accordance with the second switching signal input from the outside A second control signal for switching to either the operation or the scan test operation is generated.

  The scan flip-flop circuit of the invention of Patent Document 2 relates to the invention of a two-phase clock type scan circuit. The hardware amount of this scan circuit is 9 inverter circuits, 12 transfer circuits, 4 2-input NAND circuits, 2 3-input OR circuits, and corresponds to a total of 74 transistors. The delay from the clock terminal to the data output is large because the OR circuit, a total of four transfer circuits, an inverter circuit, and a total of two NAND circuits are routed.

Patent Document 3 (Japanese Patent Laid-Open No. 2007-187458) discloses an invention relating to a scan flip-flop circuit.
The flip-flop circuit for scanning according to the invention of Patent Document 3 includes a latch circuit portion, a hold portion, a first output node, and a second output node. Here, the hold unit captures the internal state of the latch circuit unit based on the control signal and holds the output state. The first output node outputs a first output signal based on the output state. The second output node outputs a second output signal based on the internal state. The latch circuit unit sets an internal state based on the first input signal and the second input signal.

  The scan flip-flop circuit of the invention of Patent Document 3 relates to the invention of a two-phase clock type scan circuit. The amount of hardware of this scan circuit is 14 inverter circuits and 10 transfer circuits, corresponding to a total of 48 transistors. In this scan circuit, the data held in the master latch circuit is output via two inverter circuits when the transfer circuit is opened by clock transition. At this time, the driving force from the inverter circuit located in the preceding stage is further reduced by another transfer circuit in the preceding stage of the transfer circuit. Accordingly, the delay from clock signal deviation to data output increases.

Japanese Patent No. 3587248 Japanese Patent No. 3535855 JP 2007-187458 A

  An object of the present invention is to provide a scan flip-flop circuit that operates at a higher speed while suppressing an increase in delay time, and an integrated circuit scan method using the scan flip-flop circuit.

  The scan flip-flop circuit according to the present invention is built in an arbitrary integrated circuit, and scans the integrated circuit by a one-phase clock method. The scan flip-flop circuit includes a data signal inverter circuit section and a first latch circuit section. Here, the data signal inverter circuit section is for inputting a data signal. The first latch circuit section is connected to the data signal inverter circuit section. The first latch circuit unit includes a first transfer circuit unit and a first inverter circuit unit. Here, the first transfer circuit unit is connected to the data signal inverter circuit unit. The first inverter circuit unit is connected to the first transfer circuit unit. The first transfer circuit unit controls signal transmission between the output of the data signal inverter circuit unit and the input of the first inverter circuit unit in accordance with a predetermined control signal.

  An integrated circuit scanning method using a one-phase clock method according to the present invention includes: (a) a step of inputting a data signal in the data signal inverter circuit unit; and (b) a data signal inverter circuit unit in the first latch circuit unit. And storing a signal based on the output signal of. Step (b) includes (b-1) a step of controlling signal transmission between both ends of the first transfer circuit unit according to a predetermined control signal, and (b-2) the first transfer circuit unit. And a step of inputting the output signal of the data signal inverter circuit section to the first inverter circuit section.

  An integrated circuit that undergoes a scan test employs a one-phase clock system that can operate at high speed even in the normal mode. Further, the number of transfer circuits arranged between the data signal input inverter circuit and the inverter circuit in the master latch circuit section for inputting the signal from the data signal input inverter circuit is reduced to one. By realizing one transfer circuit passing number, the setup time of the data path can be set to the same level as that of the circuit without scanning.

  The best mode for carrying out a scan flip-flop circuit according to the present invention will be described below with reference to the accompanying drawings.

  LSI (Large Size Integrated Circuit) in recent years has continued to increase in scale and density. For this reason, it is impossible to test or diagnose an LSI unless it is an LSI on which an easy-to-test design is mounted. As a technique for facilitating the test, first, the flip-flop circuits in the circuit are connected in a chain and designed so as to operate as a shift register. At the time of testing, the value of the flip-flop circuit can be arbitrarily controlled and observed from the outside using this shift function. This method is called a scan path method. In order to test an LSI using the scan path method, a plurality of scan latch circuits or a plurality of scan flip-flop circuits are provided in the LSI as test flip-flop circuits. At this time, the shift register is formed by connecting the output terminal of the logic cone in the LSI and the test input terminal of the subsequent flip-flop circuit in a chain.

  FIG. 4 is a circuit diagram for explaining a test circuit for testing an LSI by a scan path method using a scan latch circuit. This test circuit includes six scan latch circuits 91, 92, 93, 94, 95, 96, two logic cones 80, 81, and three latch circuit portions (LHT) 84, 85, 86. . However, the total number of the scan latch circuits 91 to 96 and the latch circuits 84 to 86 is merely an example, and may be another numerical value.

  In the first scan latch circuit 91, the second scan latch circuit 92, and the third scan latch circuit 93, the respective data signal output units (OUT) are connected to the first logic cone 80. ing. The first logic cone 80 and the second logic cone 81 include a first latch circuit (LHT) 84, a second latch circuit (LHT) 85, and a third latch circuit (LHT) 86. And connected to the second logic cone 81. Here, the three latch circuits (LHT) 84 to 86 are connected in parallel between the two theoretical cones 80 and 81. The second logic cone 81 is connected to each data signal input section (DAT) in the fourth scan latch circuit 94, the fifth scan latch circuit 95, and the sixth scan latch circuit 96. Has been. The scan data output units (SOT) in the first to fifth scan latch circuits 91 to 95 are connected to the shift signal input units (SFT) in the second to sixth scan latch circuits 92 to 96, respectively. Has been.

  FIG. 7 is a circuit diagram for explaining a test circuit for testing an LSI by a scan path method using a scan flip-flop circuit. This test circuit includes six scan flip-flop circuits 101, 102, 103, 104, 105, 106 and a logic cone 83. However, the total number of scan flip-flop circuits is merely an example, and other numerical values may be used.

  In the first scan flip-flop circuit 101, the second scan flip-flop circuit 102, and the third scan flip-flop circuit 103, each data signal output unit (OUT) is connected to the logic cone 83. ing. In the fourth scan flip-flop circuit 104, the fifth scan flip-flop circuit 105, and the sixth scan flip-flop circuit 106, the respective data signal input units (DAT) are connected to the logic cone 83. ing. The data signal output units (OUT) in the first, second, fourth, and fifth scan flip-flop circuits 101, 102, 104, and 105 are for the second, third, fifth, and sixth scans, respectively. The flip-flop circuits 102, 103, 105, and 106 are connected to the shift signal input units (SFT), respectively.

  In addition to the normal operation function that operates as a normal flip-flop circuit, the scan flip-flop circuit inputs a scan signal, which is a test pattern signal, from the SIN terminal, and inputs a clock slower than the normal operation from the clock terminal CLK. Thus, the circuit has a scan operation function that operates as a flip-flop circuit.

  FIG. 1 is a circuit diagram of a scan latch circuit according to the present invention. The latch circuit includes a data signal input circuit unit 1, a scan signal input circuit unit 2, a master latch circuit unit 3, a slave latch circuit unit 4, a clock signal shift signal input circuit unit 5, and a data output circuit unit 6. And a scan output circuit unit 7.

  The data signal input circuit unit 1 includes a data signal input unit (DAT) 11 and an inverter circuit (INV4) 12.

  The scan signal input circuit unit 2 includes a scan signal input unit (SIN) 21, an inverter circuit (INV5) 22, and a transfer circuit (TG2) 23. The transfer circuit (TG2) 2 includes a CKB signal input unit 231 and a CKT signal input unit 232.

  The master latch circuit unit (LLT) 3 includes a transfer circuit (TG4) 31, an inverter circuit (INV6) 32, an inverter circuit (INV7) 34, a transfer circuit (TG3) 35, and a transfer circuit (TG7) 33. It has. The transfer circuit (TG4) 31 includes a CDB signal input unit 313 and a CDT signal input unit 314. The transfer circuit (TG3) 35 includes a CKT signal input unit 351 and a CKB signal input unit 352. The transfer circuit (TG 7) 33 includes a CDT signal input unit 333 and a CDB signal input unit 334.

  The slave latch circuit unit (LHT) 4 includes a transfer circuit (TG5) 41, an inverter circuit (INV9) 42, an inverter circuit (INV10) 44, and a transfer circuit (TG6) 43. The transfer circuit (TG5) 41 includes a CKT signal input unit 411 and a CKB signal input unit 412. The transfer circuit (TG6) 43 includes a CKB signal input unit 431 and a CKT signal input unit 432.

  The clock signal shift signal input circuit unit 5 includes a clock signal input unit (CLK) 51, an inverter circuit (INV1) 53, a CKB signal output unit (CKB) 574, an inverter circuit (INV2) 54, and a CKT signal output unit. (CKT) 573, two-input NOR circuit (NOR) 56, shift signal input unit (SFT) 52, SFT signal output unit (SFT) 575, inverter circuit (INV3) 55, and SFB signal output unit (SFB) 576.

  The data output circuit unit 6 includes an inverter circuit (INV8) 61 and a data output unit (OUT) 62.

  The scan output circuit unit 7 includes an inverter circuit (INV11) 71 and a scan output unit (SOT) 72.

  Summing up the above components, this scanning latch circuit comprises 11 inverter circuits, 6 transfer circuits, and 1 2-input NOR circuit. Since the inverter circuit corresponds to 2 transistors, the transfer circuit corresponds to 2 transistors, and the 2-input NOR circuit corresponds to 4 transistors, the hardware amount of this scan latch circuit corresponds to 38 transistors.

Next, the connection relationship between the various components will be described.
In the data signal input circuit unit 1, the data signal input unit (DAT) 11 is connected to the input of the inverter circuit (INV 4) 12. The output of the inverter circuit (INV4) 12 is connected to the transfer circuit (TG4) 31. The SFB signal input unit 131 is connected to the SFB signal output unit 576. The SFT signal input unit 132 is connected to the SFT signal output unit 575.

  In the scan signal input circuit unit 2, the scan signal input unit (SIN) 21 is connected to the input of the inverter circuit (INV 5) 53. The output of the inverter circuit (INV5) 53 is connected to the transfer circuit (TG2) 23. On the other hand, the transfer circuit (TG2) 23 is connected to the transfer circuit (TG1) 13 and the transfer circuit (TG4) 31. The SFT signal input unit 233 is connected to the SFT signal output unit 575. The SFB signal input unit 234 is connected to the SFB signal output unit 576.

  In the master latch circuit unit (LLT) 3, the transfer circuit (TG 4) 31 is connected to the input of the inverter circuit (INV 6) 32, the transfer circuit (TG 3) 35, and the input of the inverter circuit (INV 6) 61. . The output of the inverter circuit (INV6) 32 is connected to the input of the inverter circuit (INV7) 34 and the transfer circuit (TG5) 41. The output of the inverter circuit (INV7) 34 is connected to the transfer circuit (TG3) 35. On the other hand, the transfer circuit (TG3) 35 is connected to the transfer circuit (TG7) 33. On the other hand, the transfer circuit (TG7) 33 is connected to the transfer circuit (TG4) 31, the input of the inverter circuit (INV6) 32, and the input of the inverter circuit (INV8) 61. The two CDB signal input units (CDB) 313 and 334 are connected to the CDB signal output unit 572. Two CDT signal input units (CDT) 314 and 333 are connected to a CDT signal output unit (CDT) 571. The CKT signal input unit 351 is connected to the CKT signal output unit 573. The CKB signal input unit 352 is connected to the CKB signal output unit 574.

  In the slave latch circuit unit (LHT) 4, the transfer circuit (TG 5) 41 is connected to the input of the inverter circuit (INV 9) 32 and the transfer circuit (TG 6) 43. The output of the inverter circuit (INV9) 42 is connected to the input of the inverter circuit (INV10) 44 and the input of the inverter circuit (INV11) 71. The output of the inverter circuit (INV10) 44 is connected to the transfer circuit (TG6) 43. The two CKT signal input units 411 and 432 are connected to the CKT signal output unit 573. The two CKB signal input units 412 and 431 are connected to the CKB signal output unit 574.

In the clock signal shift signal input circuit unit 5, the clock signal input unit (CLK) 51 is connected to the input of the inverter circuit (INV 1) 53 and the first input unit of the two-input NOR circuit (NOR) 56. The output of the inverter circuit (INV1) 53 is connected to the CKB signal output unit 574 and the input of the inverter circuit (INV2) 54. The output of the inverter circuit (INV2) 54 is connected to the CKT signal output unit 573.
The shift signal input unit (SFT) 52 is connected to a second input unit of a two-input NOR circuit (NOR) 56. The output of the 2-input NOR circuit (NOR) 56 is connected to the CDB signal output unit (CDB) 572 and the input of the inverter circuit (INV3) 55. The output of the inverter circuit (INV3) 55 is connected to a CDT signal output unit (CDT) 571.

  In the data output circuit unit 6, the output of the inverter circuit (INV 8) 61 is connected to the data output unit (OUT) 62.

  In the scan output circuit unit 7, the output of the inverter circuit (INV 11) 71 is connected to the scan output unit (SOT) 72.

Next, the operation of the scan latch circuit in this circuit diagram will be described.
In the clock signal shift signal input circuit unit 5, the inverter circuit (INV1) 53 receives a CLK (clock) signal and generates and outputs a CKB signal. The inverter circuit (INV2) 54 receives the CKB signal and generates and outputs a CKT signal. The inverter circuit (INV3) 55 receives the SFT (shift) signal and generates and outputs the SFB signal. A two-input NOR circuit (NOR) 56 receives the CLK signal and the SFT signal and generates and outputs a CDB signal. The inverter circuit (INV3) 55 receives the CDB signal and generates and outputs a CDT signal.

  In the data signal input circuit unit 1, the inverter circuit (INV4) 12 receives the DAT signal and generates and outputs a DTB signal.

  In the scan signal input circuit unit 2, the inverter circuit (INV5) 22 receives the SIN signal and generates and outputs the SIB signal. The transfer circuit (TG2) receives the SIB signal, and generates and outputs the W05 signal by passing the SIB signal when the condition of CKB = 1 is satisfied.

  In the master latch circuit unit (LLT) 3, the transfer circuit (TG 4) 31 receives the DTB signal and, when the condition of CDB = 1 is satisfied, passes the DTB signal and generates and outputs the LM signal. The inverter circuit (INV6) 32 receives the LM signal and generates and outputs the W02 signal. The inverter circuit (INV7) 34 receives the W02 signal and generates and outputs the W01 signal. The transfer circuit (TG3) 35 receives the W01 signal and, when the condition of CKT = 1 is satisfied, passes the W01 signal and generates and outputs the W05 signal. The transfer circuit (TG2) 23 and the transfer circuit (TG3) 35 are controlled by CKB and CKT which are exclusive signals. Therefore, since both transfer circuits 23 and 35 operate exclusively with each other, the SIB signal and the W01 signal do not compete as the W05 signal. The transfer circuit (TG7) 33 receives the W05 signal and, when the condition of CDT = 1 is satisfied, passes the W05 signal and generates and outputs an LM signal. The transfer circuit (TG4) 31 and the transfer circuit (TG7) 33 are controlled by CDB and CDT which are exclusive signals. Therefore, since both transfer circuits 31 and 33 operate exclusively with each other, the DTB signal and the W05 signal do not compete as the LM signal.

  In the data output circuit unit 6, the inverter circuit (INV8) 61 receives the LM signal and generates and outputs the output signal of the data output unit (OUT) 62.

  In the slave latch circuit section (LHT) 4, the transfer circuit (TG5) 41 receives the W02 signal, and when the condition of CKT = 1 is satisfied, passes the W02 signal and generates and outputs the LS signal. The inverter circuit (INV9) 42 receives the LS signal and generates and outputs the W12 signal. The inverter circuit (INV10) 44 receives the W12 signal and generates and outputs the W11 signal. The transfer circuit (TG6) 43 receives the W11 signal and, when the condition of CKB = 1 is satisfied, passes the W11 signal and generates and outputs the LS signal. The transfer circuit (TG5) 41 and the transfer circuit (TG6) 43 are controlled by the CKB signal and the CKT signal which are exclusive signals. Therefore, since both transfer circuits 41 and 43 operate exclusively with each other, the W02 signal and the W11 signal do not compete as the LS signal.

  In the scan output circuit unit 7, an inverter circuit (INV11) 71 receives the W12 signal and generates and outputs an SOT output signal.

  FIG. 5 is a truth table of the scan latch circuit according to the present invention. It can be confirmed that the output of the scan latch circuit according to the present invention is the same as that of a general scan latch circuit.

  FIG. 9 is a time chart for explaining the operation of the scan latch circuit according to the present invention. In this time chart, the horizontal axis represents the passage of time, and the vertical axis represents the binary value in each signal.

  In this description, a timing value is added by 1 for each of Low and High of the CLK signal.

  The SFT signal, DAT signal, and SIN signal are input signals. In this description, the timing at which these input signals change is determined as follows. That is, the SFT signal changes from “0 → 1” at timing 4. The DAT signal changes from “0 → 1” at timing 3 and changes from “1 → 0” at timing 5. The SIN signal changes from “0 → 1” at timing 7.

  In the data signal input circuit unit 1, the DTB signal delays the DAT signal by the delay of the inverter circuit (INV 4) 12. Similarly, in the scan signal input circuit section 2, the SIB signal also delays the SIN signal by the delay of the inverter circuit (INV 5) 22.

  In the clock signal shift signal input circuit unit 5, at timing 1 and timing 3, since CLK = 0 and SFT = 0, CDB = 1. Therefore, the DTB signal is set as the LM signal in the master latch circuit unit (LLT). At timing 1, since the DTB signal is “1”, “1” is set as the LM signal. At timing 3, since the DTB signal is “0”, “0” is set as the LM signal.

  Similarly, at timing 5 and timing 7, since CLK = 0 and SFT = 0, CDB = 1 and the W05 signal is set as the LM signal. At timing 5, since the W05 signal is “1”, “1” is set as the LM signal. At timing 7, since the W05 signal is “0”, “0” is set as the LM signal.

  Also, at timing 2, timing 4, timing 6 and timing 8, since CLK = 1, CDT = 1 and the W05 signal is set as the LM signal.

  That is, when CLK = 0, the DTB signal or SIB signal is selected according to the state of the SFT signal and set as the LM signal. The selected signal is set as an LM signal at the timing when the selected signal is changed. Therefore, it does not change in signal synchronized with the clock edge, but changes at an arbitrary timing between clock edges. In the data output circuit portion, a signal is output as the OUT signal with a delay of the inverter circuit (INV8) 61.

  In the slave latch circuit 4, when CLK = 1, the LM signal is set as the LS signal. When CKT = 1, the LM signal is fixed to Low or High. Therefore, the LS signal changes to a signal determined to be Low or High in synchronization with the clock edge. In the scan output circuit unit 7, the signal is output as the SOT signal after being delayed by the inverter circuit (INV 11) 71.

  FIG. 2 is a circuit diagram of a scan flip-flop circuit according to the present invention. This scan flip-flop circuit is equivalent to the scan latch circuit described in FIG. 1 with the scan output circuit unit 7 removed and the data output circuit unit 6 moved thereto. That is, the scan output signal (SOT) in FIG. 1 is used as the data output signal (OUT) and the scan output signal (SOT). The other parts in the circuit diagram of FIG. 2 are the same as those in FIG.

  This scan flip-flop circuit includes ten inverter circuits, six transfer circuits, and one two-input NOR circuit. Since the inverter circuit corresponds to 2 transistors, the transfer circuit corresponds to 2 transistors, and the 2-input NOR circuit corresponds to 4 transistors, the hardware amount of this scan latch circuit corresponds to 38 transistors.

  FIG. 8 is a truth table of the scan flip-flop circuit according to the present invention. It can be confirmed that the output of the scan latch circuit according to the present invention is the same as that of a general scan flip-flop circuit.

  Next, the operation of the scan flip-flop circuit of FIG. 2 will be described. The time chart for explaining the operation of the scan flip-flop circuit of FIG. 2 is equivalent to the time chart of FIG. 9 in which the OUT signal is deleted and the SOT signal is replaced with the OUT signal. The other parts of the operation of the scan flip-flop circuit of FIG. 2 are the same as the operation of the scan latch circuit of FIG.

  A normal operation and a scan operation in the test circuit of the scan latch circuit or the scan flip-flop circuit will be described.

  In the normal operation, the input signal from the DAT pin is selected by the transfer circuit TG1, held by the master latch circuit and the slave latch circuit, and then output by the OUT signal. After that, it is input to the DAT of the subsequent flip-flop circuit via the logic cone and operates as a functional circuit.

  In the scan operation, scan data from the SIN pin is selected by the transfer circuit TG2, held by the master latch circuit and the slave latch circuit, and then output by the OUT signal. Thereafter, it is input to the SIN of the flip-flop circuit in the subsequent stage to form a shift register and operate as a scan circuit.

  In the related art described above, when the data flow in the normal operation is set from the data pin to the master latch circuit, it passes through the two transfer circuits TG1 and TG4. For this reason, the signal attenuation is large and the delay is deteriorated. Therefore, in the present invention, the number of passing through the transfer circuit in normal operation is reduced. In the present invention, since the number of transfer circuits in the data flow up to the master latch circuit in the normal operation is reduced to one, the speed is increased as compared with the scanning circuit of the related art.

  As described above, in the one-phase clock scan latch circuit according to the present invention, the scan data is connected to the feedback path of the master latch circuit. By doing so, the transfer circuit of the data path can be reduced, and a circuit having almost the same setup value as the non-scanning latch circuit is realized.

  The first feature of the present invention relating to the scan latch circuit of FIG. 1 will be described. In order to improve the data path delay, a circuit system in which the scan data is connected to the feedback path of the master latch circuit (LLT) 3 instead of connecting the scan data to the data path is adopted. Here, the data path is a path toward the input of the inverter circuit (INV6) 32 through the data signal input circuit unit 1 and the transfer circuit (TG4) 31, as shown in the figure.

  The transfer circuit (TG4) 31 in the data path is controlled by a 2-input NOR circuit having CLK and SFT as inputs. This is because the logic is opened when ¬CLK & ¬ SFT = 1 (the logical product of the inversion of the CLK signal and the inversion of the SFT signal is "1"). The data output signal outputs data (OUT) of the master latch circuit, and the scan output signal outputs data (SOT) of the slave latch circuit.

  The second feature of the present invention relating to the scan flip-flop circuit of FIG. 2 will be described. In order to improve the data path delay, a circuit system in which the scan data is connected to the feedback path of the master latch circuit (LLT) 3 instead of connecting the scan data to the data path is adopted. The transfer circuit (TG4) 31 in the data path is controlled by a 2-input NOR circuit having CLK and SFT as inputs. This is because the logic is opened when ¬CLK & ¬ SFT = 1 (the logical product of the inversion of the CLK signal and the inversion of the SFT signal is "1"). The data output and the scan output are the same slave latch circuit data.

  The difference between the one-phase clock scan latch circuit of feature 1 and the one-phase clock scan flip-flop circuit of feature 2 will be described. Regarding the data output logic, the scan latch circuit is the master latch circuit output, whereas the scan flip-flop circuit is the slave latch circuit output. That is, the data output timing is different.

  The data processing timing will be described. By inserting latch circuits 84 to 86 (timing adjustment mechanism corresponding to slave latch circuits) between the data output pins of the scan latch circuits 91 to 93 and the data input pins of the subsequent scan latch circuits 94 to 96, Timing is adjusted (see FIG. 4). Considering this latch circuit, the timings of the scan latch circuit and the scan flip-flop circuit are the same.

  The scan processing timing will be described. Since the scan latch circuit and the scan flip-flop circuit output the result of the slave latch circuit, the timing is the same.

FIG. 1 is a circuit diagram of a scan latch circuit according to the present invention. FIG. 2 is a circuit diagram of a scan flip-flop circuit according to the present invention. FIG. 3 is a circuit diagram of a one-phase clock scan latch circuit according to the related art. FIG. 4 is a circuit diagram for explaining a test circuit for testing an LSI by a scan path method using a scan latch circuit. FIG. 5 is a truth table of the scan latch circuit according to the present invention. FIG. 6 is a circuit diagram of a scan flip-flop circuit according to the related art. FIG. 7 is a circuit diagram for explaining a test circuit for testing an LSI by a scan path method using a scan flip-flop circuit. FIG. 8 is a truth table of the scan flip-flop circuit according to the present invention. FIG. 9 is a time chart for explaining the operation of the scan latch circuit according to the present invention. FIG. 10 is a time chart for explaining the operation of the scan latch circuit according to the related art.

Explanation of symbols

1 Data signal input circuit 11 Data signal input (DAT)
12 Inverter circuit (INV4)
13 Transfer circuit (TG1)
131 SFB signal output unit (SFB)
132 SFT signal output unit (SFT)
2 Scan signal input circuit section 21 Scan signal input section (SIN)
22 Inverter circuit (INV5)
23 Transfer circuit (TG2)
231 CKB signal output unit (CKB)
232 CKT signal output unit (CKT)
233 SFT signal output unit (SFT)
234 SFB signal output unit (SFB)
3 Master latch circuit (LLT)
31 Transfer circuit (TG4)
311 CKB signal input section (CKB)
312 CKT signal input section (CKT)
313 CDB signal input unit (CDB)
314 CDT signal input section (CDT)
32 Inverter circuit (INV6)
33 Transfer circuit (TG7)
331 CKT signal input section (CKT)
332 CKB signal input section (CKB)
333 CDT signal input section (CDT)
334 CDB signal input section (CDB)
34 Inverter circuit (INV7)
35 Transfer circuit (TG3)
351 CKB signal input section (CKB)
352 CKT signal input section (CKT)
4 Slave latch circuit (LHT)
41 Transfer circuit (TG5)
411 CKT signal input section (CKT)
412 CKB signal input section (CKB)
42 Inverter circuit (INV9)
43 Transfer circuit (TG6)
431 CKB signal input section (CKB)
432 CKT signal input section (CKT)
44 Inverter circuit (INV10)
5 Clock signal shift signal input circuit section 51 Clock signal input section (CLK)
52 Shift signal input section (SFT)
53 Inverter circuit (INV1)
54 Inverter circuit (INV2)
55 Inverter circuit (INV3)
56 NOR circuit (NOR1)
571 CDT signal output section (CDT)
572 CDB signal output unit (CDB)
573 CKT signal output section (CKT)
574 CKB signal output unit (CKB)
575 SFT signal output unit (SFT)
576 SFB signal output unit (SFB)
6 Data output circuit section 61 Inverter circuit (INV8)
62 Data output section (OUT)
7 Scan output circuit 71 Inverter circuit (INV11)
72 Scan output unit (SOT)
80 to 82 Logic cone 83 to 85 Slave latch circuit (LHT)
91-96 Latch circuits 101-103 Flip-flop circuit

Claims (11)

A scan flip-flop circuit built in any integrated circuit,
A data signal inverter circuit section for inputting a data signal;
A first latch circuit connected to the data signal inverter circuit,
The first latch circuit unit includes:
A first transfer circuit connected to the output of the data signal inverter circuit;
A first inverter circuit unit connected to the output of the first transfer circuit unit;
The first transfer circuit unit controls signal transmission between the output of the data signal inverter circuit unit and the input of the first inverter circuit unit according to a predetermined control signal,
A scanning flip-flop circuit that scans the integrated circuit using a one-phase clock method. The scan flip-flop circuit according to claim 1,
An inverter circuit unit for a scan signal for inputting the scan signal;
A scan signal transfer circuit connected to an output of the scan signal inverter circuit; and
A clock signal shift signal input circuit unit for inputting the clock signal and the shift signal;
The first latch circuit unit includes:
A second inverter circuit portion connected to the output of the first inverter circuit portion;
A second transfer circuit connected to the output of the second inverter circuit;
A third transfer circuit unit connected to the output of the second transfer circuit unit and connected to the input of the first inverter circuit unit;
The scan signal transfer circuit portion is connected to a connection portion between the second transfer circuit portion and the third transfer circuit portion,
The clock signal shift signal input circuit unit outputs a predetermined control signal according to a combination of the clock signal and the shift signal,
The first transfer circuit unit, the second transfer circuit unit, the third transfer circuit unit, and the first-stage scan signal transfer circuit unit are configured to select the first inverter circuit according to the control signal. A signal to be supplied to the unit is selected and determined from the output signal of the data signal inverter circuit unit, the output signal of the previous scan signal inverter circuit unit, and the output signal of the second inverter circuit unit. Flip-flop circuit. The scan flip-flop circuit according to claim 1,
The clock signal shift signal input circuit unit is
A scan flip-flop circuit comprising a predetermined logic circuit unit that generates and outputs a control signal corresponding to a combination of the clock signal and the shift signal. The scan flip-flop circuit according to claim 1,
A second latch circuit unit connected to a subsequent stage of the first latch circuit unit;
A first output circuit unit connected to a subsequent stage of the second latch circuit unit,
The first output circuit unit is a scan flip-flop circuit that outputs a data output signal. The scan flip-flop circuit according to any one of claims 1 to 4,
The amount of hardware obtained by converting each circuit part into the number of transistors is 38 transistors or less. The scan flip-flop circuit according to claim 1,
A second latch circuit unit connected to a subsequent stage of the first latch circuit unit;
A first output circuit unit connected to a subsequent stage of the second latch circuit unit; and a second output circuit unit connected to an input of the first inverter circuit unit;
The first output circuit unit outputs a scan output signal,
The second output circuit unit is a scan latch circuit that outputs a data output signal. The scan flip-flop circuit according to any one of claims 1 to 5,
A shift register circuit comprising a plurality of the scan flip-flop circuits. The scan latch circuit according to claim 6,
A shift register circuit comprising a plurality of scan latch circuits. The shift register circuit according to claim 7 or 8,
An integrated circuit comprising the shift register circuit. (A) in the data signal inverter circuit section, inputting a data signal;
(B) storing a signal based on an output signal of the data signal inverter circuit section in the first latch circuit section;
The step (b)
(B-1) controlling signal transmission between both ends of the first transfer circuit unit according to a predetermined control signal;
(B-2) In the first transfer circuit unit, the step of inputting the output signal of the data signal inverter circuit unit to the first inverter circuit unit. . The integrated circuit scan method according to claim 10, wherein the one-phase clock method is used.
(C) In the scan signal inverter circuit unit, inputting a scan signal;
(D) the clock signal shift signal input circuit unit further comprises a step of selecting and determining a signal supplied to the first inverter circuit unit based on a combination of the clock signal and the shift signal;
The step (d)
(D-1) inputting the clock signal and the shift signal;
(D-2) generating and outputting a control signal according to a combination of the clock signal and the shift signal;
(D-3) connected to the output of the first transfer circuit unit, the second transfer circuit unit and the third transfer circuit unit in the first latch circuit unit, and the scan signal inverter circuit unit A step of controlling a transfer circuit portion for a scan signal with the control signal;
(D-4) By the control of step (d-3), the signal supplied to the first inverter circuit unit is changed between the output signal of the data signal inverter circuit unit and the previous scan signal inverter circuit unit. An integrated circuit scanning method using a one-phase clock method, comprising: selecting and determining an output signal and an output signal of the second inverter circuit unit.

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