JP4384792B2 - Input/Output Circuit - Google Patents

Description

[0001]
[Technical field to which the invention pertains]
The present invention relates to an input/output circuit for connecting an external circuit in an integrated circuit of a microcontroller.
[0002]
2. Description of the Related Art
In general, input/output circuits used in microcontrollers such as microcomputers are designed to allow one external connection interface to be switched between being used as an input or output circuit for digital signals by rewriting a function setting register with a program. Furthermore, some input/output circuits can be used as an output circuit for address signals and data signals for an external bus, or as an input circuit with a pull-up as a secondary function.
[0003]
FIG. 2 is a configuration diagram showing an example of a conventional input/output circuit.
This input/output circuit is incorporated into an integrated circuit of a microcomputer and has function setting registers such as an input/output control register 12, a secondary function control register 13, an output data register 14, and a pull-up control register 15 connected to an internal bus 11.
[0004]
The input/output control register 12 holds a control command for input mode or output mode given via the internal bus 11 to switch between input/output operations. The output data register 14 holds output data given via the internal bus 11 in the output mode. The secondary function control register 13 holds control information for switching whether to output data in the output data register 14 or to output an address signal or the like given as a secondary function in the output mode. The pull-up control register 15 holds control information for whether to pull up an input terminal in the input mode.
[0005]
The output side of the output data register 14 is connected to a first input side of a selector 16, and a secondary function output signal such as an address signal is provided to a second input side of the selector 16. The selector 16 selects and outputs a signal on the first or second input side based on control information provided from the secondary function control register 13. The output side of the selector 16 is connected to an input/output terminal 18 for connecting to an external circuit via an output buffer 17. When an output mode signal OUT provided from the input/output control register 12 becomes level "H", the output buffer 17 amplifies the output signal of the selector 16 to drive an external circuit connected to the input/output terminal 18. When the output mode signal OUT is level "L", the output side of the output buffer 17 becomes a high impedance state and is disconnected from the input/output terminal 18.
[0006]
The input side of an input buffer 19 is connected to the input/output terminal 18. When an input mode signal IN provided from the input/output control register 12 becomes "H", the input buffer 19 outputs an input signal provided from an external circuit to the input/output terminal 18 to the internal bus 11. When the input mode signal IN is "L", the output side of the input buffer 19 becomes a high impedance state and is disconnected from the internal bus 11.
[0007]
The input mode signal IN output from the input/output control register 12 and the output signal from the pull-up control register 15 are provided to the input side of a two-input negative AND gate (hereinafter referred to as "NAND") 20. The output side of the NAND 20 is connected to the gate of a P-channel MOS transistor (hereinafter referred to as "PMOS") 21. The source of the PMOS 21 is connected to the power supply potential VDD, and the drain is connected to the input/output terminal 18.
[0008]
In such an input/output circuit, by setting the input mode or output mode in the input/output control register 12 via the internal bus 11, it is possible to select whether the circuit will function as an input circuit or an output circuit.
When the input mode is set, a control signal can be further set in the pull-up control register 15 to make the PMOS 21 conductive, thereby pulling up the input/output terminal 18. An input signal input from an external circuit to the input/output terminal 18 is then provided to the internal bus 11 via the input buffer 19.
[0009]
On the other hand, when the output mode is set, a control signal is further set in the secondary function control register 13, so that either the data stored in the output data register 14 or the secondary function output signal can be selected and output by the selector 16. The output signal selected by the selector 16 is power-amplified by the output buffer 17 and output to the input/output terminal 18, which drives an external circuit connected to the input/output terminal 18.
[0010]
[Problem to be solved by the invention]
However, the conventional input/output circuits have the following problems.
FIG. 3 is a signal waveform diagram showing signal timing when writing data to a static random access memory (hereinafter referred to as "SRAM").
[0011]
As shown in Fig. 3, in an SRAM, an address signal must first be applied, and once a certain address sense time has elapsed and the state of the decoder and other components within the SRAM has been established, a strobe signal must be applied (set to "L"). After the data signal to be written is applied, the strobe signal must be set to "H" after a certain data setup time has elapsed. Furthermore, even after the strobe signal has become "H", the address signal must not be changed for a certain address hold time. Furthermore, the data signal must not be changed for a certain data hold time. If these timing conditions are not met, data cannot be written correctly to the SRAM.
[0012]
2, if a timing mismatch occurs between the output signal and the input side external circuit due to the external circuit and the connection method connected to the input/output terminal 18, the external circuit may become unusable. For example, when an SRAM is connected as an external circuit, there is a problem that access becomes difficult unless appropriate timing conditions are met between the address signal, data signal, and strobe signal, which are output signals from the input/output terminal 18. Furthermore, if the capabilities of the input buffer 19 and the output buffer 17 do not match the input/output conditions of the external circuit connected to the input/output terminal 18, there is a problem that data errors and a decrease in data speed occur due to degradation of the input/output waveform.
[0013]
The present invention solves the problems associated with the conventional techniques and provides an input/output circuit that allows adjustment of input/output signal timing and selection of input/output conditions.
[0014]
[Means for solving the problem]
In order to solve the above problem, the invention according to claim 1 of the present invention is an input/output circuit that is incorporated into an integrated circuit of a microcontroller and inputs/outputs data or signals between an external circuit connected via an input/output terminal of the integrated circuit, and is provided with a delay means for delaying the data or the signal to be output to the input/output terminal, the delay means having a plurality of delay elements connected in series, generating a plurality of delayed signals delayed by a plurality of delay times using the outputs of any of the plurality of delay elements, and outputting any one of the generated delayed signals or a signal combining any of the plurality of delayed signals as an output signal to the input/output terminal based on control information.
[0015]
The invention according to claim 2 is characterized in that the input/output circuit according to claim 1 further comprises a plurality of output buffers having different driving capabilities, and an output means for outputting the data or the signal to the input/output terminal via an output buffer preselected from among the output buffers.
[0016]
The invention according to claim 3 is characterized in that, in the input/output circuit according to claim 1 or 2, it further comprises an input means having a plurality of input buffers having different input characteristics, and inputting the data or the signal given to the input/output terminal through an input buffer preselected from among the input buffers.
[0017]
According to a fourth aspect of the present invention, in the input/output circuit of the third aspect, the input/output terminal is selectively controlled to be set to a predetermined potential or not in an input mode.
[0018]
The invention of claim 5 is characterized in that, in the delay means in the input/output circuit described in any one of claims 1 to 4, the control information has first information and second information, and further has a selection output stage that selectively outputs some of the multiple delay signals based on the first information, and a signal generation stage that generates a combined signal based on the signals selectively output from the selection output stage, and outputs the output signal that is a combination of any one of the multiple delay signals or any several of the multiple delay signals based on the second information.
[0019]
The invention according to claim 6 is characterized in that in the input/output circuit according to claim 5, the signal generation stage has a first signal generation circuit that generates and outputs the combined signal based on the selectively output signals, and a second signal generation circuit that generates and outputs the output signal from the output of the first signal generation circuit based on the second information.
[0020]
[0023]
FIG. 1 is a block diagram of an input/output circuit showing an embodiment of the present invention, and elements common to those in FIG. 2 are given the same reference numerals.
This input/output circuit is incorporated in an integrated circuit such as a microcomputer. This input/output circuit has function setting registers, an output switching register 22 and an input switching register 23, in addition to the input/output control register 12, secondary function control register 13, output data register 14, and pull-up control register 15 similar to those in Fig. 2. These registers are connected to the internal bus 11.
[0021]
The input/output control register 12 holds a control command for specifying an input mode or an output mode given via the internal bus 11, and switches between input/output operations. When the input mode is set in the input/output control register 12, an input mode signal IN of "H" is output, and when the output mode is set, an output mode signal OUT of "H" is output.
[0022]
The output data register 14 holds output data provided via the internal bus 11 in the output mode. The secondary function control register 13 holds control information for switching whether to output data in the output data register 14 or to output an address signal or the like provided as a secondary function in the output mode. The pull-up control register 15 holds control information for whether to pull up the input/output terminal 18 in the input mode.
[0023]
On the other hand, the output switching register 22 holds a control signal for switching the drive capability of the output buffer. For example, when an output buffer with high drive capability is selected, the output switching register 22 holds a control signal of "H", and when an output buffer with low drive capability is selected, the output switching register 22 holds a control signal of "L". The input switching register 23 holds a control signal for switching the input level of the input buffer. For example, when an input buffer with a TTL level is selected, the input switching register holds a control signal of "H", and when an input buffer with a CMOS level is selected, the input switching register holds a control signal of "L".
[0024]
The output side of the output data register 14 is connected to a first input side of a selector 16, and a secondary function output signal, such as an address signal, is provided to a second input side of the selector 16. The selector 16 selects and outputs a signal on the first or second input side based on control information provided from the secondary function control register 13. The output side of the selector 16 is connected to an input side of a delay means (e.g., a delay circuit) 30.
[0025]
The delay circuit 30 delays the output signal of the selector 16 based on a control signal provided from the internal bus 11, and the output side of the delay circuit 30 is connected to the input sides of the output buffers 17a and 17b, which have different driving capabilities. The output sides of the output buffers 17a and 17b are connected to the input/output terminals 18 for connecting to external circuits. When the control signal provided to the control terminals of the output buffers 17a and 17b is "H", the output signal of the delay circuit 30 is amplified to drive the external circuit connected to the input/output terminals 18. When the control signal provided to the control terminals of the output buffers 17a and 17b is "L", the output side of the output buffers 17a and 17b is in a high impedance state and is disconnected from the input/output terminals 18. The output buffer 17a has a larger driving capability than the output buffer 17b.
[0026]
A decoder 24 is connected to the output side of the output switching register 22. The decoder 24 is composed of, for example, two-input logical product gates (hereinafter referred to as "AND") 24a, 24b and an inverter 24c. When the output mode signal OUT output from the input/output control register 12 is "H", the decoder 24 outputs "H" signals from the ANDs 24a, 24b in response to the "H" and "L" output signals of the output switching register 22. The output sides of the ANDs 24a, 24b are connected to the control terminals of the output buffers 17a, 17b, respectively.
[0027]
The input sides of input buffers 19a and 19b are connected to the input/output terminal 18. The input buffers 19a and 19b output an input signal given to the input/output terminal 18 from an external circuit to the internal bus 11 when a control signal given to the control terminal becomes "H". When the control signal is "L", the output sides of the input buffers 19a and 19b are in a high impedance state and are disconnected from the internal bus 11. The input buffer 19a is a TTL level buffer, and the input buffer 19b is a CMOS level buffer.
[0028]
A decoder 25 is connected to the output side of the input switching register 23. The decoder 25 is composed of, for example, two-input ANDs 25a and 25b and an inverter 25c. When the input mode signal IN output from the input/output control register 12 is "H", the decoder 25 outputs "H" signals from the ANDs 25a and 25b in response to the "H" and "L" output signals of the input switching register 23. The outputs of the ANDs 25a and 25b are connected to the control terminals of the input buffers 19a and 19b, respectively.
[0029]
The input mode signal IN output from the input/output control register 12 and the output signal from the pull-up control register 15 are provided to the input side of a two-input NAND 20. The output side of the NAND 20 is connected to the gate of a PMOS 21. The source of the PMOS 21 is connected to a power supply potential VDD, and the drain is connected to the input/output terminal 18. The input/output control register 12, the pull-up control register 15, the NAND 20, and the PMOS 21 are configured to selectively control whether or not the input/output terminal 18 is set to a predetermined potential (pull-up) during the input mode.
[0030]
FIG. 4 is a circuit diagram showing an example of the delay circuit 30 in FIG.
The delay circuit 30 includes a delay element 31a to which the output signal of the selector 16 is given, a delay element 31b connected to the latter stage, and a register 32 to which a control signal is set from the internal bus 11. The register 32 has output terminals A, B, and C for outputting first information of the control information, and an output terminal D for outputting second information of the control information. The input and output sides of the delay element 31a and the output side of the delay element 31a are each connected to a first input side of a selection output stage consisting of two-input AND gates 33a, 33b, and 33c. The second input sides of the AND gates 33a to 33c are each connected to the output terminals A, B, and C of the register 32.
[0031]
The output sides of the ANDs 33a to 33c are connected to the input sides of a first signal generating circuit consisting of a three-input logical OR gate (hereinafter referred to as "OR") 34 and an AND 35. The output sides of the OR 34 and the AND 35 are connected to the first input sides of two-input ANDs 36 and 37, respectively. The second input side of the AND 36 is connected to the output terminal D of the register 32, and the second input side of the AND 37 is connected to the output terminal D of the register 32 via an inverter 38. Furthermore, the output sides of the ANDs 36 and 37 are connected to the input sides of a two-input OR 39, and the output side of this OR 39 is connected to the input sides of the output buffers 17a and 17b. The ANDs 36, 37 and the OR 39 form a second signal generating circuit, and the second signal generating circuit and the first signal generating circuit form a signal generating stage.
[0032]
FIG. 5 is a signal waveform diagram for explaining the function of the delay circuit 30 in FIG.
In Fig. 4, the input signal S16 is delayed by delay elements 31a and 31b to become signals S31a and S31b, respectively. These signals S16, S31a and S31b correspond to bits 0 (A), 1 (B) and 2 (C) of the 4-bit control signal output from output terminals A, B, C and D of the register 32. Signals in which the corresponding bits of the control signal are set to a logical value "1" are selected by ANDs 33a to 33c, and signals S34 and S35 are output from ORs 34 and 35, respectively. The signals S34 and S35 are input to a selector composed of ANDs 36 and 37, an inverter 38 and an OR 39, and one of them is selected according to the control signal output from output terminal D of the register 32 and output as signal S39.
[0033]
5, when the signal S16 rises at time t1, the signal S16 is delayed by the delay element 31a, and the signal S31a rises at time t2. The signal S31a is further delayed by the delay element 31b, and the signal S31b rises at time t3.
When the signal S16 falls at time t4, the signal S16 is delayed by the delay element 31a, and the signal S31a falls at time t5. The signal S31a is further delayed by the delay element 31b, and the signal S31b falls at time t6.
[0034]
Here, if the set value of register 32 is "0001", a signal having the same timing as signal S16 is output as signal S39. If the set value of register 32 is "0010", a signal having the same timing as signal S31a is output as signal S39, and if the set value of register 32 is "0100", a signal having the same timing as signal S31b is output as signal S39.
[0035]
Furthermore, by setting two bits out of bits 0 to 2 of register 32 to "1", a signal having a timing that combines signal S16 and signals S31a and S31b can be output as signal S39. For example, if the set value of register 32 is "0011", signal S39 having a width from time t1 to t5 is obtained. If the set value of register 32 is "0101", signal S39 having a width from time t1 to t6 is obtained, and if the set value is "0110", signal S39 having a width from time t2 to t6 is obtained.
[0036]
Furthermore, by setting bit 3 of register 32 to "1", inverted signals of signals S16, S31a, S31b, and S39 designated by bits 0 to 2, respectively, can be obtained.
[0037]
Next, the operation of FIG. 1 will be explained separately for (I) an input mode and (II) an output mode.
(I) Input Mode When an input mode is set in the input/output control register 12 via the internal bus 11, the input mode signal IN output from this input/output control register 12 becomes "H". On the other hand, the output mode signal OUT output from the input/output control register 12 becomes "L", both output signals of the decoder 24 become "L", and the output sides of the output buffers 17a and 17b become high impedance and are disconnected from the input/output terminal 18.
[0038]
Also, based on whether the output condition of the external circuit connected to the input/output terminal 18 is the TTL level or the CMOS level, the input switching register 23 is set to "1" or "0." When the input switching register 23 is set to "1," the output signal of the AND 25a of the decoder 25 becomes "H," and the input/output terminal 18 is connected to the internal bus 11 via the TTL-level input buffer 19a. On the other hand, when the input switching register 23 is set to "0," the output signal of the AND 25b of the decoder 25 becomes "H," and the input/output terminal 18 is connected to the internal bus 11 via the CMOS-level input buffer 19b.
[0039]
Furthermore, when the input/output terminal 18 is pulled up, "1" is set in the pull-up control register 15. This causes the output signal of the NAND 20 to go "L", turning the PMOS 21 on and pulling up the input/output terminal 18. On the other hand, when "0" is set in the pull-up control register 15, the output signal of the NAND 20 goes "H", turning the PMOS 21 off and not pulling up.
[0040]
In this way, the input level is set by the input switching register 23 to select either the input buffer 19a or 19b, and the pull-up control register 15 is used to set whether or not pull-up is required, thereby setting this input/output circuit to an input circuit that meets the interface conditions of the external circuit. An input signal input to the input/output terminal 18 is then output to the internal bus 11 via the input buffer 19a or 19b.
[0041]
(II) Output Mode When an output mode is set in the input/output control register 12 via the internal bus 11, the output mode signal OUT output from this input/output control register 12 becomes "H". On the other hand, the input mode signal IN output from the input/output control register 12 becomes "L", both output signals of the decoder 25 become "L", and the output sides of the input buffers 19a and 19b become high impedance and are disconnected from the internal bus 11. Furthermore, the output signal of the NAND 20 becomes "H", and the PMOS 21 becomes off.
[0042]
Also, the output switching register 22 is set to "1" or "0" based on the magnitude of the load of the external circuit connected to the input/output terminal 18. When the output switching register 22 is set to "1", the output signal of the AND 24a of the decoder 24 becomes "H", and the output side of the delay circuit 30 is connected to the input/output terminal 18 via the output buffer 17a with a large driving capacity. On the other hand, when the output switching register 22 is set to "0", the output signal of the AND 24b of the decoder 24 becomes "H", and the output side of the delay circuit 30 is connected to the input/output terminal 18 via the output buffer 17b with a small driving capacity.
[0043]
Furthermore, a delay time is set in the delay circuit 30 from the internal bus 11, and a control signal for outputting either the data stored in the output data register 14 or the secondary function output signal is set in the secondary function control register 13.
As a result, the output signal selected by the selector 16 is delayed by a predetermined time in the delay circuit 30, amplified to a predetermined power by the output buffer 17a or 17b, and output to the input/output terminal 18, thereby driving an external circuit connected to this input/output terminal 18.
[0044]
As described above, the input/output circuit of this embodiment has the following advantages (1) to (3).
(1) In the output mode, the delay circuit 30 can delay the output timing of secondary function output signals such as address signals and output data by any time, or increase or decrease the time of the output signal. As a result, when this input/output circuit is used as an external bus function, it is possible to change the output timing of address signals, data signals, strobe signals, etc. output as secondary functions, and to match the timing conditions of external circuits such as SRAM connected to the input/output terminals 18. In addition, when used as an output circuit for a clock-synchronized serial port, it is possible to change the timing of the transmission clock signal and transmission data, so that the transmission data setup time and transmission data hold time can be adjusted to match the peripheral device of the external circuit with which the circuit is to communicate. This allows an increase in the types of external circuits that can be connected.
[0045]
(2) The device has output buffers 17a and 17b with different drive capabilities, and an output switching register 22 and a decoder 24 for switching between these output buffers 17a and 17b. As a result, when the drive capability of the output buffer 17b with a smaller capacity is insufficient due to an increase in the load capacity of the external circuit, the device can be switched to the output buffer 17a with a larger drive capability to eliminate delays caused by dulling of the output signal. In addition, since the drive capability can be changed even when using the external bus function and the synchronous serial port, which are secondary functions, the device can adjust the setup time and hold time of the output signal by speeding up or slowing down the rise of the output signal.
[0046]
(3) It has input buffers 19a and 19b with different input levels, and also has an input switching register 23 and a decoder 25 for switching between these input buffers 19a and 19b. This allows it to match the output conditions of external circuits, so that it is possible to increase the types of external circuits that can be connected. In addition, since the input level can be changed even when using the external bus function and synchronous serial port, it is possible to adjust the setup time and hold time of the input signal by speeding up or slowing down the capture of the input signal.
[0047]
The present invention is not limited to the above-described embodiment, and various modifications are possible. Examples of such modifications include the following (a) to (f).
(a) The configuration of the delay circuit 30 is not limited to that shown in FIG. 4. In other words, the number of delay elements can be increased to three or more to increase the number of delay times that can be set. This widens the time adjustment range and further increases the types of external circuits that can be connected. In addition, by using a counter as the delay element, the delay time can be adjusted on a clock basis.
[0048]
(b) In the delay circuit 30, the delay time can be programmed by the register 32, but a switch or an external terminal for setting the delay time may be provided instead of the register 32. Such a setting switch or the like is effective in the case of an input/output circuit that needs to operate normally before the initial setting when the power is turned on.
[0049]
(c) The number of selectable input buffers and output buffers is not limited to two. For example, the type of input buffer is not limited to those that perform level conversion such as TTL and CMOS, and a Schmitt circuit having a hysteresis characteristic can also be used. By increasing the number and types of input buffers and output buffers, the types of connectable external circuits can be further increased.
[0050]
(d) The pull-up control register 15 and the output switching register 22 are not used at the same time, so they can be shared. Alternatively, the input switching register 23 and the output switching register 22 may be shared.
[0051]
(e) If the output level of the external circuit is determined to be, for example, CMOS, there is no need to provide two types of input buffers. In that case, the input switching register 23 and the decoder 25 are not required.
[0052]
(f) If there is no need to switch the drive capability for an external circuit, there is no need to provide two types of output buffers. In that case, the output switching register 22 and the decoder 24 are not required.
[0053]
Effect of the Invention
As described above in detail, the first invention (invention according to claims 1, 5, and 6) has a delay means for delaying data or signals to be output to an input/output terminal. This delay means is configured to generate a plurality of delayed signals, generate a signal by combining some of these delayed signals, and output this as an output signal to the input/output terminal, so that the signal to be output to the input/output terminal can be delayed by any amount of time, or the time of the output signal can be increased or decreased. This makes it possible to match the timing conditions of an external circuit, and to adapt to various memories and peripheral circuits with different timing conditions, enabling efficient input/output operations.
[0054]
According to the second aspect of the present invention (invention related to claims 2, 5 and 6) , there is provided an output means for outputting data or a signal via an output buffer having a preselected driving capability, which makes it possible to use an output buffer suited to the load capacitance of an external circuit, thereby enabling efficient input/output operations.
[0055]
According to the third aspect of the invention (inventions related to claims 3 to 6) , there is provided an input means for inputting data or signals via an input buffer having preselected input characteristics, which makes it possible to use an input buffer that matches the output conditions of an external circuit, and thus makes it possible to support various external circuits.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of an input/output circuit showing an embodiment of the present invention.
FIG. 2 is a configuration diagram showing an example of a conventional input/output circuit.
FIG. 3 is a signal waveform diagram showing signal timing when data is written to an SRAM.
4 is a circuit diagram showing an example of a delay circuit 30 in FIG. 1;
5 is a signal waveform diagram for explaining the function of the delay circuit 30 of FIG. 4. FIG.
[Explanation of symbols]
11 Internal bus 12 Input/output control register 13 Secondary function control register 14 Output data register 15 Pull-up control register 16 Selectors 17a, 17b Output buffer 18 Input/output terminals 19a, 19b Input buffer 20 NAND
21 PMOS
22 Output switching register 23 Input switching register 24, 25 Decoder

Claims (6)

An input/output circuit that is incorporated in an integrated circuit of a microcontroller and inputs/outputs data or signals between an external circuit connected via an input/output terminal of the integrated circuit,
a delay means for delaying the data or the signal to be output to the input/output terminal;
The delay means has a plurality of delay elements connected in series, generates a plurality of delayed signals delayed by a plurality of delay times using the outputs of any of the plurality of delay elements, and outputs any one of the generated delayed signals or a signal combining any of the plurality of delayed signals as an output signal to the input/output terminal based on control information. The input/output circuit according to claim 1 further comprises:
1. An input/output circuit comprising: a plurality of output buffers each having a different driving capability; and output means for outputting the data or the signal to the input/ output terminal via an output buffer previously selected from among the output buffers. The input/output circuit according to claim 1 or 2 further comprises:
1. An input/output circuit comprising: a plurality of input buffers each having a different input characteristic; and input means for inputting the data or the signal applied to the input/ output terminal through an input buffer previously selected from among the input buffers. 4. The input/output circuit according to claim 3, wherein in the input mode, it is possible to selectively control whether or not said input/output terminal is set to a predetermined potential. In the delay means,
The control information includes first information and second information, and further includes:
a selection output stage that selectively outputs some of the plurality of delayed signals based on the first information;
a signal generating stage that generates a combined signal based on the signal selectively output from the selection output stage, and outputs the output signal that is a combination of any one of the plurality of delayed signals or any of some of the plurality of delayed signals based on the second information;
5. The input/output circuit according to claim 1, further comprising: The signal generation stage comprises:
a first signal generating circuit that generates and outputs the combined signal based on the selectively outputted signals;
a second signal generating circuit that generates the output signal from an output of the first signal generating circuit based on the second information and outputs the output signal;
6. The input/output circuit according to claim 5, further comprising:

Images